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- - A Reference-Less Clock and Data Recovery Circuit Using a Pulse-Width Modulation Scheme With Improved Data Bit Error Rate Tolerance and Recovery Method thereof
- - A Reference-Less Clock and Data Recovery Circuit Using a Pulse-Width Modulation Scheme With Improved Data Bit Error Rate Tolerance and Recovery Method thereof
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机译：-使用具有改进的数据误码率容限的脉宽调制方案的无参考时钟和数据恢复电路及其恢复方法
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摘要
Disclosed is a clock-data recovery circuit and method that does not require an external reference clock of a pulse-width modulation scheme that improves data bit error tolerance. A phase-frequency detector (PFD), a charge pump (CP), a loop, and the like are provided in a clock-data recovery circuit that does not require an external reference clock of a pulse-width modulation type in which a data bit error tolerance is improved. A phase-locked loop (PLL) in which a filter, a loop filter (LF), and a voltage controlled oscillator (VCO) are sequentially connected; A divider configured by a D flip flop connected to the phase locked loop; The output clock (Clock) of the voltage-controlled oscillator is input to the clock (clk) terminal, the in terminal is applied with VDD (Logic high), and the reset terminal is applied with pulse-width modulation. A shift register (SR) for applying PWM (Pulse Width Modulation) data; An OR gate for passing an output waveform of the shift register; And a gate SR latch (GSRL) disposed behind the OR gate to form a set and a reset signal to be used as an input signal.
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