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Experimental study on BTI variation impacts in SRAM based on high-k/metal gate FinFET: From transistor level Vth mismatch, cell level SNM to product level Vmin

机译:基于高k /金属栅极FINFET的SRAM中BTI变异影响的实验研究:从晶体管级Vth错配,细胞水平SNM到产品水平VMIN

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Aging induced variability has been shaving away the design margins in advanced SRAM which may become more serious with highly scaled process node. This paper provides a systematical study of the BTI variation impacts in FinFET SRAM based on 14nm 128Mbit SRAM, including the characterization from transistor and cell level to product. For transistor level, despite the effective process optimization for BTI shifts, SRAM transistor Vth mismatch shows non-negligible increase after aging due to the intrinsic Sqrt(1/WL) BTI variability trend as time=0 variations. For cell level, BTI distribution is found to be the dominant factor comparing with the circuit level parameters such as Vdd or inverter (PU/PD) ratio in terms of read SNM shifts after aging. An empirical model of EOL SNM is further proposed for the circuit level quick evaluation and HTOL fail prevention. For product level, the FBC (Failure Bit Count) slope from cell-to-cell variation and Vmin distribution from chip-to-chip variation also show non-negligible impacts due to BTI variability. The results indicate that besides the process optimization for BTI mean shifts, reliability aware circuit design is necessity to consider intrinsic BTI variation increase with transistor scaling down.
机译:老化诱导的变化已经剃掉了高级SRAM中的设计边缘,这可能与高度缩放的过程节点变得更加严重。本文基于14nm 128Mbit SRAM提供了对FinFET SRAM的BTI变化影响的系统研究,包括从晶体管和电池水平到产品的表征。对于晶体管电平,尽管对BTI偏移有效的过程优化,但SRAM晶体管Vth错配显示由于内在的SQRT(1 / WL)BTI可变性趋势导致老化后的不可忽略的增加= 0变化。对于细胞级,发现BTI分布是与老化后读取SNM偏移的电路电平参数(如VDD或逆变器(PU / PD)比相比的主要因素。进一步提出了EOL SNM的经验模型,用于电路级快速评估和HTOL失败预防。对于产品水平,FBC(故障位计数)从细胞到电池变化和来自芯片到芯片变化的VMIN分布的斜率也表示由于BTI变异性导致的不可忽略的影响。结果表明,除了BTI平均换档的过程优化外,可靠性意识电路设计是考虑与晶体管缩放的内在BTI变化增加的必要条件。

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