Embedded FLOTOX flash on ultra-low power 55nm logic DDC platform

机译：在超低功耗55nm逻辑DDC平台上的嵌入式FLOTOX闪存

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We have successfully embedded flash memory on an ultra-low power (<;0.9V) 55nm Deeply Depleted Channel™ (DDC) platform. In spite of reduced thermal budget of DDC process, single-bit charge loss (SBCL) of flash after cycling can be optimized and is comparable to that of baseline embedded flash. We have also verified that improved variability and resultant ultra-low power digital performance of the DDC process is maintained in an embedded flash flow.

机译：我们已经成功地在超低功耗（<; 0.9V）55nm深度耗尽通道（DDC）平台上嵌入了闪存。尽管DDC工艺的热预算减少了，但可以优化循环后闪存的单位电荷损耗（SBCL），这可与基准嵌入式闪存相媲美。我们还验证了嵌入式闪存流中保持了改进的可变性以及由此产生的DDC处理的超低功耗数字性能。

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《IEEE International Electron Devices Meeting》|2013年|1-4|共4页
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Hori M.; Fujita K.; Yasuda M.; Ookoshi K.;
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2. Embedded Flash on a Low-Power 65-nm Logic Technology [J] . Fong S., Ariyoshi J., Ema T. Electron Device Letters, IEEE . 2012,第9期

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4. Embedded FLOTOX flash on ultra-low power 55nm logic DDC platform [C] . Hori M., Fujita K., Yasuda M., IEEE International Electron Devices Meeting . 2013

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Embedded FLOTOX flash on ultra-low power 55nm logic DDC platform

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