首页> 外文会议>IEEE Biennial Congress of Argentina >Implementaci#x00F3;n de un algoritmo DSOGI-PLL en una FPGA para sincronizaci#x00F3;n con la red de convertidores de potencia
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Implementaci#x00F3;n de un algoritmo DSOGI-PLL en una FPGA para sincronizaci#x00F3;n con la red de convertidores de potencia

机译:在FPGA中实现DSOGI-PLL算法以与电源转换器网络同步

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Power converters are the subject of extensive research because of their ability to work under different operating conditions, providing bidirectional power flow, high dynamic range and fast response. These advantages allow them to be used as interface between the electric grid and many high power applications such as motors, energy storage, active filters and renewable energy sources. To be able to connect to the utility grid, every power converter must be provided with a synchronization method. The synchronization algorithms are mostly based on the well known SRF-PLL (Synchronous Reference Frame Phase Locked Loop) plus some pre-filter stage that can be achieved by different algorithms of variable complexity, usually implemented on DSPs (Digital Signal Processor) or Microcontrollers. In this paper a simple and highly effective FPGA (Field Programmable Gate Array) implementation of a PLL (Phase Locked Loop) algorithm based on a DSOGI-PLL (Dual Second Order Generalized Integrator Phase Locked Loop) is presented in detail, along with the auxiliary circuitry needed to acquire the grid voltage information. Using a fast-prototype high-level synthesis tool, design time is drastically reduced without the need of any HDL (Hardware Description Language) code. Both simulation with MATLAB Simulink and experimental results on a Xilinx SoC (System on Chip), show a robust behaviour even against frequency steps, severe distortion and unbalances in the power input.
机译:功率转换器因能够在不同的工作条件下工作,提供双向功率流,高动态范围和快速响应而成为广泛研究的主题。这些优势使它们可用作电网和许多大功率应用(例如电动机,储能器,有源滤波器和可再生能源)之间的接口。为了能够连接到公用电网,必须为每个电源转换器提供同步方法。同步算法主要基于众所周知的SRF-PLL(同步参考帧锁相环)加上一些预滤波器级,这些级可以通过通常在DSP(数字信号处理器)或微控制器上实现的可变复杂度不同的算法来实现。在本文中,详细介绍了一种基于DSOGI-PLL(双二阶广义积分器锁相环)的PLL(锁相环)算法的简单高效的FPGA(现场可编程门阵列)实现。获取电网电压信息所需的电路。使用快速原型的高级综合工具,可以大大减少设计时间,而无需任何HDL(硬件描述语言)代码。使用MATLAB Simulink进行的仿真以及在Xilinx SoC(片上系统)上的实验结果均显示出了鲁棒的性能,即使在频率阶跃,严重失真和功率输入不平衡的情况下也是如此。

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