Active-mode leakage power optimization using state-preserving techniques

机译：使用状态保持技术的有源模式泄漏功率优化

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As technology sizes shrink, the developers come upon a problem of leakage currents. Among the different power reduction approaches there are power gating and clock gating, which can significantly eliminate (cut down) components of power consumption. The combined use of these approaches shows great promise. In fact, this good idea poses challenges due to some difficulties in practical integration. First, there is a need in additional control logic and timing overheads appear. Secondly, the flip-flops need to be shut down during active-mode without any loss in logic states. We examine different state-preserving techniques that can retain data of flip-flops during the power gating. All presenting techniques can achieve leakage reduction in active mode of operation for combined approach.

机译：随着技术规模的缩小，开发人员面临着泄漏电流的问题。在不同的功率降低方法中，有功率门控和时钟门控，可以显着消除（减少）功耗组件。这些方法的组合使用显示出巨大的希望。实际上，由于实际集成中存在一些困难，所以这个好主意提出了挑战。首先，需要附加的控制逻辑，并且会出现时序开销。其次，需要在活动模式期间关闭触发器，而不会损失逻辑状态。我们研究了在电源门控期间可以保留触发器数据的不同状态保留技术。对于组合方法，所有呈现技术都可以在主动操作模式下减少泄漏。

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《IEEE East-West Design Test Symposium》|2014年|1-4|共4页
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Korshunov Andrey V.; Volobuev Pavel S.;
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flip-flops; leakage currents; low-power electronics; optimisation; power consumption; active-mode leakage power optimization; clock gating; control logic; flip-flops; leakage currents; logic states; power consumption; power gating; power reduction; state-preserving techniques; timing overheads; CMOS integrated circuits; Clocks; Delays; Flip-flops; Leakage currents; Logic gates; Transistors;

机译：触发器;漏电流;低功耗电子设备;优化;功耗;有源模式泄漏功率优化;时钟门控;控制逻辑;触发器;漏电流;逻辑状态;功耗;功率门控;功耗降低;状态保护技术;定时开销; CMOS集成电路;时钟;延迟;触发器;漏电流;逻辑门;晶体管;

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1. Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs [J] . Chul-Moon Jung, Eun-Sub Lee, Huan Minh Vo, IEICE Electronics Express . 2011,第16期

机译：带有子模块电源门控的选择加法器，可减少32nm以下VLSI中的有源模式泄漏
2. Gate Sizing and V{sub}t Assignment for Active-Mode Leakage Power Reduction [J] . Feng Gao, John P. Hayes Journal of Low Power Electronics . 2006,第2期

机译：栅极尺寸调整和V {sub} t分配，可降低有源模式泄漏功率
3. Gate Sizing and V{sub}t Assignment for Active-Mode Leakage Power Reduction [J] . Feng Gao, John P. Hayes Journal of Low Power Electronics . 2006,第2期

机译：栅极尺寸调整和V {sub} t分配，可降低有源模式泄漏功率
4. Active-mode leakage power optimization using state-preserving techniques [C] . Korshunov Andrey V., Volobuev Pavel S. East-West Design Test Symposium . 2014

机译：使用状态保存技术的主动模式漏电功率优化
5. High level techniques for leakage power estimation and optimization in VLSI ASICs. [D] . Gopalakrishnan, Chandramouli. 2003

机译：VLSI ASIC中用于泄漏功率估计和优化的高级技术。
6. Optimized Power System Management Scheme for LSS PV Grid Integration in Malaysia Using Reactive Power Compensation Technique [O] . Mahesh Mohanan, Yun Ii Go 2020

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7. Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs [O] . Huan Minh Vo, Chul-Moon Jung, Eun-Sub Lee, 2011

机译：随着子块功率门控提供选择加法器，用于减少Sub-32-NM VLSI中的主动模式泄漏

Active-mode leakage power optimization using state-preserving techniques

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