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Serdes SSC ATE solution

机译：Serdes SSC ATE解决方案

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摘要

Spread-spectrum is a technique which is widely used in telecommunication and radio communication. For clock signal, this technique makes the clock signal energy distributed on the relevant frequency range rather than on the single frequency point. Thus the Electro-Magnetic-Interference (EMI) of clock is reduced. Since the clock signal is modulated by another signal, resulting in its frequency is changing, and data-rate around couples of Giga bps, Spread-spectrum clock(SSC) testing on ATE is facing challenges. Conceptually, changing clock signal does not meet under-sampling requirement. This paper solves this issue from the differentiable viewpoint getting SSC tested on ATE and get its test time meets production requirement. With this method, several 15Gbps hi-speed devices are tested on 93K PSSL digital card. In real production, this method is enhanced to get better stability while capturing the high-speed clock signal. This SSC ATE solution improved chip test coverage dramatically. It makes clock PLL module has much better stability and reliability from the benefit of implementing this testing in production.
机译：扩频是在电信和无线电通信中广泛使用的技术。对于时钟信号，此技术使时钟信号能量分配在相关频率范围上，而不是在单个频率点上。因此，减少了时钟的电磁干扰（EMI）。由于时钟信号是由另一个信号调制的，导致其频率发生了变化，并且数据速率达到了几千兆比特/对，因此在ATE上进行扩频时钟（SSC）测试面临着挑战。从概念上讲，更改时钟信号不符合欠采样要求。本文从差异化的角度解决了这一问题，并在ATE上对SSC进行了测试，使其测试时间达到了生产要求。使用此方法，已在93K PSSL数字卡上测试了多个15Gbps高速设备。在实际生产中，增强了该方法，以在捕获高速时钟信号的同时获得更好的稳定性。该SSC ATE解决方案极大地提高了芯片测试的覆盖率。由于在生产中实施了该测试，因此使时钟PLL模块具有更好的稳定性和可靠性。

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