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A study of narrow transistor layout proximity effects for 28nm Poly/SiON logic technology

机译：28nm Poly / SiON逻辑技术的窄晶体管布局邻近效应研究

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As the CMOS technology has entered the nanoscale regime, several previously negligible physical effects are becoming increasingly important as a result of aggressive layout scaling. On the other hand, today's IC chips, especially those in the mobile devices with rich functions, need to pack a huge number of transistors into a very small area. In such cases, narrow and small transistors are widely used. As small transistors have both minimum width and minimum gate length, they are more sensitive to the surrounding neighborhood and therefore more susceptible to layout proximity effects than other transistors. In this paper, layout proximity effects (LPEs) of the 28nm Poly/SiON logic technology were studied with a focus on narrow and small transistors. The LPEs include width effect, length of diffusion (LOD) effect, active area spacing effect (ASE), and well proximity effect (WPE). We found that compared with the wider/larger counterparts, the narrow/small transistors exhibited stronger layout dependence effects as expected due to the stronger environment-induced dopant re-distribution and/or stress modulation.
机译：随着CMOS技术进入纳米尺度，由于积极的布局缩放，一些以前可以忽略的物理效应变得越来越重要。另一方面，当今的IC芯片，特别是功能强大的移动设备中的IC芯片，需要在很小的区域内封装大量的晶体管。在这种情况下，窄而小的晶体管被​​广泛使用。由于小型晶体管具有最小宽度和最小栅极长度，因此它们对周围的邻域更敏感，因此比其他晶体管更容易受到布局邻近效应的影响。在本文中，研究了28nm Poly / SiON逻辑技术的布局邻近效应（LPE），重点是窄和小晶体管。 LPE包括宽度效应，扩散长度（LOD）效应，有源区域间隔效应（ASE）和阱邻近效应（WPE）。我们发现，与较宽/较大的晶体管相比，较窄/较小的晶体管表现出更强的布局依赖性效应，这是由于较强的环境引起的掺杂物重新分布和/或应力调制所致。

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