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Novel Approach to Reduce Source/Drain Series Resistance in High Performance CMOS Devices Using Self-Aligned CoWP Process for 45nm Node UTSOI Transistors with 20nm Gate Length

机译：使用20nm栅极长度的45nm节点UTSOI晶体管的自对准COMOS器件在高性能CMOS器件中降低高性能CMOS器件源/漏极串联电阻的新方法

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This paper reports a novel, non-epitaxial raised source/drain approach to decrease the parasitic series resistance in nMOSFETs fabricated on UTSOI using a selective electroless metal deposition process. A metallic layer selectively deposited in the source/drain and gate nickel or cobalt silicide regions significantly reduces the parasitic external resistance in nMOSFETs with 10nm body thickness and gate lengths down to 20nm. This approach is fully compatible with a conventional CMOS process flow for both Co and Ni silicides and eliminates the added complexity of a conventional raised source/drain approach. The extremely high deposition selectivity of the process is confirmed through gate leakage measurements.

机译：本文报道了一种新颖的非外延凸出的源/排水方法，以降低使用选择性化学金属沉积工艺在UTSOI上制造的NMOSFET中的寄生串联电阻。选择性地沉积在源/漏极和栅极镍或钴区内的金属层显着降低了NMOSFET中的寄生虫外部电阻，并且栅极长度低至20nm。该方法与用于CO和Ni硅化物的传统CMOS工艺流程完全兼容，并消除了传统凸起源/排水方法的增加的复杂性。通过栅极泄漏测量确认该过程的极高沉积选择性。

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《IEEE Symposium on VLSI Technology》|2006年||共2页
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James Pan; Anna Topol; Ingrid Shao; Dinkar Singh; Zhibin Ren; C. Y. Sung; Meikei Ieong; John Pellerin; John Iacoponi; Ming-Ren Lin;
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专利

1. Novel Approach to Reduce Source/Drain Series and Contact Resistance in High-Performance UTSOI CMOS Devices Using Selective Electrodeless CoWP or CoB Process [J] . Pan J., Topol A., Shao I., IEEE Electron Device Letters . 2007,第8期

机译：使用选择性无电极CoWP或CoB工艺减少高性能UTSOI CMOS器件中源/漏级数和接触电阻的新颖方法
2. Study on the Lateral Carrier Diffusion and Source-Drain Series Resistance in Self-Aligned Top-Gate Coplanar InGaZnO Thin-Film Transistors [J] . Sae-Young Hong, Hee-Joong Kim, Dae-Hwan Kim, Scientific reports. . 2019,第1期

机译：自对准顶栅共面薄膜薄膜晶体管中横向载波扩散和源极漏极串联电阻的研究
3. Reduced Hot-Carrier Induced Degradation of NMOS I/O Transistors with Sub-micron Source-Drain Diffusion Length for 0.11 μm Dual Gate Oxide CMOS Technology [J] . Kwang-Seng SEE, Wai-Shing LAU, Suey-Li TOH, Japanese Journal of Applied Physics. Part 1, Regular Papers & Short Notes . 2005,第4B期

机译：具有亚微米源漏扩散长度的0.11μm双栅氧化物CMOS技术可减少NMOS I / O晶体管因热载流子引起的退化
4. Novel Approach to Reduce Source/Drain Series Resistance in High Performance CMOS Devices Using Self-Aligned CoWP Process for 45nm Node UTSOI Transistors with 20nm Gate Length [C] . James Pan, Anna Topol, Ingrid Shao, IEEE Symposium on VLSI Technology . 2006

机译：使用20nm栅极长度的45nm节点UTSOI晶体管的自对准COMOS器件在高性能CMOS器件中降低高性能CMOS器件源/漏极串联电阻的新方法
5. Design, fabrication, and characterization of tungsten/silicon germanium/silicon raised single source/drains for sub-100nm CMOS and sub-70nm fully self-aligned double-gated CMOS [D] . Gan, Dong 2000

机译：低于100nm CMOS和低于70nm完全自对准双栅极CMOS的钨/硅锗/硅凸起单源/漏极的设计，制造和表征
6. Study on the Lateral Carrier Diffusion and Source-Drain Series Resistance in Self-Aligned Top-Gate Coplanar InGaZnO Thin-Film Transistors [O] . Sae-Young Hong, Hee-Joong Kim, Dae-Hwan Kim, -1

机译：自对准顶栅共面InGaZnO薄膜晶体管的横向载流子扩散和源漏串联电阻的研究
7. 13.1 A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-κ Metal Gate CMOS [O] . Gianfranco Gerosa, Steve Curtis, Bo Jiang, 2011

机译：13.1低于1W至2W的低功耗IA处理器，适用于45nmHi-κ金属门CMOS的移动互联网设备和超移动PC

Novel Approach to Reduce Source/Drain Series Resistance in High Performance CMOS Devices Using Self-Aligned CoWP Process for 45nm Node UTSOI Transistors with 20nm Gate Length

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