首页> 外文会议>IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics >Impact on the Physical Design flow, due to Repositioning the Macros in the Floorplan stage of Video decoder at Lower Technologies
【24h】

Impact on the Physical Design flow, due to Repositioning the Macros in the Floorplan stage of Video decoder at Lower Technologies

机译:由于在Lower Technologies的视频解码器的平面图阶段重新定位了宏,因此对物理设计流程的影响

获取原文

摘要

As IC process geometries scaled down to the Deep Sub Micron territory, industry's face severe challenges of Timing, Run time, Congestion, QOR, Yield & manufacturing limitations. In this paper, mostly discuss on how macro placing in floorplan affect Timing, Congestion, QOR, DRC's of every stage in the design flow. Two test cases are considered to compare their congestion, utilization ratio, QOR, DRC's and finding out which macro placings is efficient for design requirement.
机译:随着IC工艺几何尺寸缩小到Deep Sub Micron(深亚微米)领域,行业面临时序,运行时间,拥塞,QOR,良率和制造限制的严峻挑战。本文主要讨论布局图中的宏布局如何影响设计流程中每个阶段的时序,拥塞,QOR和DRC。考虑了两个测试用例,以比较它们的拥塞,利用率,QOR,DRC,并找出哪些宏布局对于设计要求是有效的。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号