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An efficient FPGA based implementation of forward integer transform and quantization algorithm of H.264

机译:基于FPGA的前向整数变换和H.264量化算法实现的高效实现

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Integer transformation has been used to exploit the spatial redundancy of input video in the recent video coding standard H.264. The standard has also introduced novel algorithms for quantization and inverse quantization processes. In this paper, we present efficient hardware architectures for real-time implementation of forward integer transform and quantization algorithms used in H.264 video codec. The proposed hardware architecture for forward transform is based on a reconfigurable datapath with minimum number of adders/subtractors and shifters. This hardware is designed to be used as part of a complete H.264 video coding system for realtime applications. Using Xilinx Virtex-4 technology, the proposed architecture for forward transform has been verified to run at a maximum frequency of 210 MHz.
机译:整数转换已被用于利用最近视频编码标准H.264中输入视频的空间冗余。该标准还引入了用于量化和逆量化过程的新颖算法。在本文中,我们提供了高效的硬件架构,用于实时实现H.264视频编解码器中使用的前向整数变换和量化算法。用于前向变换的所提出的硬件架构基于具有最小数量的加法器/减法器和移位器的可重新配置数据路径。此硬件旨在用作实时应用程序的完整H.264视频编码系统的一部分。使用Xilinx Virtex-4技术,已验证了用于前进变换的建议架构以以210 MHz的最大频率运行。

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