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Design and Implementation of a Software Defined Radio GNSS Receiver Based on OpenCL

机译：基于OpenCL的软件定义无线电GNSS接收机的设计与实现

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During the design and implementation of digital circuits for various applications, mapping of algorithms to different hardware components is a central task to achieve best in class performance (e.g., low power consumption per position fix, position accuracy and position deviation for satellite navigation receivers). During the last decade software defined radio receivers (SDRs) and Field Programmable Gate Array (FPGA) based receivers gain more and more importance during the prototyping phase and for receivers with an expected low volume production. These receivers are also of special interest during the introduction of new signals and frequency bands. FPGA based receivers allow a flexible design and the implementation of highly parallel digital logic and software based processing at the same time. The fundamental drawback of FPGA based GNSS receiver solutions is the high design complexity and the enlarged design space. In this context the design space describes the number of parameters the designer has to consider, to optimize the final design for a given application. Successful navigation in this design space, requires experience in various disciplines (e.g. Radio Frequency (RF) engineering, signal processing, GNSS algorithm design). The main idea of this paper is to ease the design, simulation and cost optimization of Software Defined Radio (SDR) GNSS receivers, implemented on standard PCs, Graphical Processing Units (GPUs) and FPGAs. The idea is to describe the receiver architecture and the receiver specifications at a very high and thus understandable level. During the next step a compiler maps the different receiver signal processing blocks to the existing hardware (i.e. General Purpose Computer (GPC), FPGA or GPU). Using this approach, the most time consuming parts (i.e. design description and specification) have to be done only once and the design is based on a single code base.
机译：在针对各种应用的数字电路的设计和实现期间，将算法映射到不同的硬件组件是实现一流性能（例如，每个定位的低功耗，卫星导航接收器的位置精度和位置偏差）的中心任务。在过去的十年中，基于软件定义的无线电接收器（SDR）和基于现场可编程门阵列（FPGA）的接收器在原型设计阶段以及预期批量生产的接收器中变得越来越重要。在引入新信号和频带期间，这些接收器也特别受关注。基于FPGA的接收器允许同时进行灵活的设计以及高度并行的数字逻辑和基于软件的处理的实现。基于FPGA的GNSS接收器解决方案的基本缺点是设计复杂性高和设计空间大。在这种情况下，设计空间描述了设计人员必须考虑的参数数量，以优化给定应用程序的最终设计。在此设计空间中成功导航需要各种学科的经验（例如，射频（RF）工程，信号处理，GNSS算法设计）。本文的主要思想是简化在标准PC，图形处理单元（GPU）和FPGA上实现的软件定义无线电（SDR）GNSS接收器的设计，仿真和成本优化。这个想法是在很高的层次上描述接收器的体系结构和接收器的规格，因此可以理解。在下一步中，编译器将不同的接收器信号处理模块映射到现有硬件（即通用计算机（GPC），FPGA或GPU）。使用这种方法，最耗时的部分（即设计说明和规范）只需完成一次，并且设计基于单个代码库。

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