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A Resource-saving Method for Implementation of High-Performance Time-to-Digital Converters in FPGA

机译：在FPGA中实现高性能时间数字转换器的一种节省资源的方法

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摘要

In field programmable gate array (FPGA) based time-to-digital converters (TDC), the prevailing time interpolation is propagating the hit signal along the tapped delay line (TDL), which status is sampled to be encoded as the sub-clock timestamp. The TDLs in all current TDC designs have lengths that guarantee the total propagating time on TDLs larger than one system clock period, which results in a more complicated encoder and unnecessary logic resource consumption. In this paper, we propose to shorten the TDL length by half and combine it to a novel bubble-proof encoding scheme with an aim to make the TDC resource-saving without losing any performance. Such two identical TDC channels have been implemented in a Xilinx Kintex-7 FPGA. Their performances are evaluated with an average RMS precision of 9.7 ps for measuring time-intervals from 0 to 20 ns and the measurement throughput of 277 M events per second, which are equivalent to the TDCs implemented in our previous work using the long TDLs. The consumption of logic resources is demonstrated to be 80% of the original. This resource-saving advantage of the proposed TDC is important to applications that require highly integrated multi-channel TDC systems.
机译：在基于现场可编程门阵列（FPGA）的时间数字转换器（TDC）中，主要的时间插值方法是沿抽头延迟线（TDL）传播命中信号，该状态信号被采样以编码为子时钟时间戳记。当前所有TDC设计中的TDL的长度都可以保证TDL上的总传播时间大于一个系统时钟周期，这会导致编码器更加复杂，并且逻辑资源不必要地消耗。在本文中，我们建议将TDL长度缩短一半，并将其结合到一种新颖的防气泡编码方案中，以期在不损失任何性能的情况下节省TDC资源。这样的两个相同的TDC通道已在Xilinx Kintex-7 FPGA中实现。以9.7 ps的平均RMS精度对0至20 ns的时间间隔进行测量，以及每秒277 M事件的测量吞吐量来评估其性能，这与我们先前使用长TDL进行的工作中实现的TDC相当。事实证明，逻辑资源的消耗是原始资源的80％。提议的TDC的这种节省资源的优势对于需要高度集成的多通道TDC系统的应用非常重要。

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