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首页> 外文会议>2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design >An analytical drain current model for GS GAA MOSFET including interfacial traps
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An analytical drain current model for GS GAA MOSFET including interfacial traps

机译：包含界面陷阱的GS GAA MOSFET的分析漏电流模型

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摘要

It's widely recognized that Gate-All-Around (GAA) MOSFETs are considered among the most probable choices to continue CMOS performance boost beyond the conventional scaling frontiers. Such device offers the best controllability of short-channel effects claimed to be the predominant factor limiting how far the downscaling can be achieved. However, the lack of analytic compact models for degraded drain current can easily be notified in literature. Therefore, in this work we investigate the immunity of GAA MOSFET against the hotcarrier-induced degradation effect after considering the step-function approximation for interface charge distribution. The importance of including a high-k layer into the device architecture is also studied; the damaged device model presented in this work provides a simple and accurate approach for simulating the circuit behavior after hot-carrier damage.
机译：众所周知，全能栅极（GAA）MOSFET被认为是使CMOS性能继续提升到传统扩展领域之外的最有可能的选择之一。这种设备提供了最佳的短通道效果可控性，据称这是限制缩小效果的主要因素。但是，在文献中很容易发现缺乏用于降低漏极电流的解析紧凑模型的信息。因此，在这项工作中，我们在考虑了界面电荷分布的阶跃函数近似之后，研究了GAA MOSFET对热载流子引起的退化效应的抗扰性。还研究了在设备架构中包括高k层的重要性。这项工作中提出的损坏的器件模型为模拟热载流子损坏后的电路行为提供了一种简单而准确的方法。

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