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首页> 外文会议>International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design >An analytical drain current model for GS GAA MOSFET including interfacial traps
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An analytical drain current model for GS GAA MOSFET including interfacial traps

机译：GS GAA MOSFET的分析漏极电流模型，包括界面陷阱

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摘要

It's widely recognized that Gate-All-Around (GAA) MOSFETs are considered among the most probable choices to continue CMOS performance boost beyond the conventional scaling frontiers. Such device offers the best controllability of short-channel effects claimed to be the predominant factor limiting how far the downscaling can be achieved. However, the lack of analytic compact models for degraded drain current can easily be notified in literature. Therefore, in this work we investigate the immunity of GAA MOSFET against the hotcarrier-induced degradation effect after considering the step-function approximation for interface charge distribution. The importance of including a high-k layer into the device architecture is also studied; the damaged device model presented in this work provides a simple and accurate approach for simulating the circuit behavior after hot-carrier damage.
机译：它普遍认识到，在最可能的选择中考虑了全面的门（GaA）MOSFET，以继续超越传统的缩放前沿的CMOS性能升高。这种装置提供了短信效应的最佳可控性，声称是限制较令人抵制的主要因素的主要因素。然而，在文献中可以很容易地通知缺乏用于降低的漏极电流的分析紧凑型号。因此，在这项工作中，我们在考虑界面电荷分布的阶梯函数近似之后，研究GaA MOSFET对热载波引起的劣化效果的影响。还研究了包括高k层进入设备架构的重要性;本工作中提供的受损设备模型提供了一种简单准确的方法，可以在热载波损坏后模拟电路行为。

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