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Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm Node

机译：垂直磁隧道结阵列的工艺优化，用于超过7 nm节点的最后一级缓存

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This paper demonstrates systematic process optimization of perpendicular magnetic tunnel junction (pMTJ) by hardware, unit-process, and material stack design. TMR of 200% at RA 5 Ohm·μm^{2, H_SAF ~ 8 kOe, and 10-time tunability of Hc were achieved at the film level. After patterning, 10^{-6 write error rate was reached at 0.4 pJ, V_BD was as high as 1600 mV at 20 ns pulse width, and excellent device stability against 400°C BEOL baking was demonstrated. The device performance along with the process capability to make MTJ array at 88 nm pitch provides opportunities for LLC applications.}}

机译：本文通过硬件，单元过程和材料堆栈设计演示了垂直磁隧道结（pMTJ）的系统过程优化。在RA 5 Ohm·μm处的TMR为200％ ^{2
， H
_{SAF
在薄膜水平上获得了约8 kOe的Hc和10倍的Hc可调性。图案化后，10
^{-6
写入错误率达到0.4 pJ，V
_{BD
脉冲宽度为20 ns时，其最高为1600 mV，并且证明了在400°C的BEOL烘烤下具有出色的器件稳定性。器件性能以及以88 nm间距制造MTJ阵列的工艺能力为LLC应用提供了机会。}}}}

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《IEEE Symposium on VLSI Technology》|2018年|117-118|共2页
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Lin Xue; Chi Ching; Alex Kontos; Jaesoo Ahn; Xiaodong Wang; Renu Whig; Hsin-wei Tseng; James Howarth; Sajjad Hassan; Hao Chen; Mangesh Bangar; Shurong Liang; Rongjun Wang; Mahendra Pakala;
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关键词
Magnetic tunneling; Tunneling magnetoresistance; Films; Optimization; Performance evaluation; Error analysis; Couplings;

机译：磁隧穿;隧道磁阻;薄膜;优化;性能评估;误差分析;耦合;

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专利

1. Low-Current High-Speed Spin-Transfer Switching in a Perpendicular Magnetic Tunnel Junction for Cache Memory in Mobile Processors [J] . Saida D., Shimomura N., Kitagawa E., Magnetics, IEEE Transactions on . 2014,第11期

机译：垂直磁隧道结中的低电流高速自旋转移开关，用于移动处理器中的高速缓存
2. Perpendicular STT_RAM cell in 8 nm technology node using Co_1/Ni_3(111)||Gr_2||Co_1/Ni_3(111) structure as magnetic tunnel junction [J] . Ali Varghani, Ali Peiravi, Farshad Moradi Journal of magnetism and magnetic materials . 2018,第APRa期

机译：使用Co_1 / Ni_3（111）|| Gr_2 || Co_1 / Ni_3（111）结构作为磁隧道结的8 nm技术节点中的垂直STT_RAM单元
3. Model of inter-cell interference phenomenon in 10 nm magnetic tunnel junction with perpendicular anisotropy array due to oscillatory stray field from neighboring cells [J] . Ohuchida Satoshi, Endoh Tetsuo Japanese journal of applied physics . 2018,第6期

机译：10nm磁隧道结的电池间干扰现象与邻近电池振荡杂交场引起的垂直各向异性阵列
4. Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm Node [C] . Lin Xue, Chi Ching, Alex Kontos, IEEE Symposium on VLSI Technology . 2018

机译：垂直磁隧道结阵列的过程优化，用于超级高速缓存超过7nm节点
5. Perpendicular Magnetic Tunnel Junctions with MgO Tunnel Barrier [D] . Almasi, Hamid. 2017

机译：具有MgO隧道势垒的垂直磁性隧道结
6. Tunneling-Magnetoresistance Ratio Comparison of MgO-Based Perpendicular-Magnetic-Tunneling-Junction Spin Valve Between Top and Bottom Co2Fe6B2 Free Layer Structure [O] . Du-Yeong Lee, Seung-Eun Lee, Tae-Hun Shim, 2016

机译：Co2Fe6B2上下自由层结构之间基于MgO的垂直-电磁-隧道-结自旋阀的隧道-磁阻比比较
7. Magnetic reversal and thermal stability of CoFeB perpendicular magnetic tunnel junction arrays patterned by block copolymer lithography [O] . Kun-Hua Tu, Eduardo Fernandez, Hamid Almasi, 2018

机译：嵌段共聚物光刻图案化CoFeB垂直磁隧道结阵列的磁反转和热稳定性

Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm Node

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