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Power Optimization of a 32-Bit ALU Using Distributed Clock Gating Technique

机译：使用分布式时钟门控技术的32位ALU的功率优化

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In this paper, a distributed clock gating technique is applied to a 32-bit ALU. The ALU design performs all the fundamental arithmetic and logical operations based on the selection of the operations. The system operates at 250 MHz clock frequency. Clock gating is the predominant technique applied to circuits to avoid unnecessary switching activity, leading to power consumptions. Here, the ALU designed is segregated as two functional modules, and the clock gating is applied, leading to distributed clock gating. The design is analyzed for gray code and random test patterns, and it is observed that gray code data representation consumes less power. The 32-bit ALU is implemented for a 45 nm technology using CADENCE tool. Simulation results show that the hierarchical and distributed clock gating techniques aid in power reduction to nearly 45% to 50%, depending on the transitions on the input signals with an increase in area by 2% to 3%. The gray code input test patterns provide better power reduction as compared to traditional random inputs.
机译：在本文中，将分布式时钟门控技术应用于32位ALU。 ALU设计基于对操作的选择执行所有基本算术和逻辑运算。系统以250 MHz时钟频率运行。时钟门控是应用于电路的主要技术，以避免不必要的切换活动，导致功耗。这里，设计的ALU被偏析为两个功能模块，并且施加时钟门控，导致分布式时钟门控。分析设计进行灰色码和随机测试模式，观察到灰色代码数据表示消耗更少的功率。使用Cadence工具实现32位ALU为45 nm技术实现。仿真结果表明，等级和分布式时钟门控技术有助于降低电力降低至近45％至50％，这取决于输入信号上的过渡，面积增加2％至3％。与传统随机输入相比，格雷码输入测试模式提供更好的功率降低。

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