A compact VLSI design for recursive neural networks with hardware annealing capability

机译：具有硬件退火能力的递归神经网络的紧凑型VLSI设计

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In this paper, we present a compact CMOS VLSI design for recursive neural networks with the capability of hardware annealing. Locally-connected recursive neural networks are a class of analog nonlinear networks which can solve many important optimization, and signal processing problems and is suitable for VLSI implementation because of its low demand on inter-cell connections. Hardware annealing, which is a paralleled version of effective mean-field annealing in analog networks, is a highly-efficient method to find global optimal solutions of recursive neural networks. A two-neuron prototype chip to demonstrate the functionality of hardware annealing is designed, analyzed and implemented in 2.0 /spl mu/m CMOS technology using mixed-signal design methodology through MOSIS. For circuit reliability and compactness, a unit current of 6 /spl mu/A is used. The cell density is 505 cells/cm/sup 2/ and the cell time constant time is designed to be 0.3 /spl mu/s. Laboratory experimental results to show the behavior of this two neuron chip was produced with annealing control signals from a function generator.

机译：在本文中，我们提出了一个紧凑的CMOS VLSI设计与硬件退火能力递归神经网络。本地连接的递归神经网络是一类模拟非线性网络，这可以解决许多重要的优化，并且信号处理问题，并适合于VLSI实现由于其对小区间的连接需求较低。硬件退火，这是在模拟网络的有效平均场退火的并联版本，是要找到递归神经网络的全局最优解决方案的高效方法。的两神经元芯片原型展示硬件退火的功能被设计，分析和通过使用MOSIS混合信号设计方法在2.0 / SPL亩/米的CMOS技术实现。对于电路的可靠性和紧凑性，则使用/ 6 / SPL亩单元电流A。细胞密度是505个细胞/ cm / SUP 2 /和电池时间常数的时间被设计成0.3 / SPL亩/秒。实验室实验结果显示这两神经元芯片的与从函数发生器退火控制信号制作的行为。

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《IEEE International Conference on Neural Networks》|1995年||共6页
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Chou E.Y.; Sheu B.J.; Institute of Electric and Electronic Engineer;
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中图分类自动化技术、计算机技术;
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A compact VLSI design for recursive neural networks with hardware annealing capability

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