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首页> 外文会议>International Conference on VLSI Design >A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units
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A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units

机译：一种新的低功率误差检测逻辑，用于浮点单元中的不精确零预测器

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摘要

In floating point addition unit, adder and normalization decides the critical path delay. By predicting the shift amount prior to the adder's output the delay introduced by the normalization can be reduced. This prediction is done using a technique called Leading Zero Anticipator (LZA). LZA algorithms are divided into exact and inexact categories. Most of the existing algorithms are inexact in nature which predicts the shift amount with a possible error of 1 bit. So, these inexact LZA algorithms need an error detection circuit. This paper proposes an error detection logic implemented in parallel with adder and using a part hardware of LZA resulting in reduction of both area and power consumption by 35%-39% and 44%-48% respectively when compared with that of general LZA and error detection circuit.
机译：在浮点加法单元中，加法器和归一化决定了关键路径延迟。通过预测加法器输出之前的换档量，可以减少归一化引入的延迟。使用称为前导零预期（LZA）的技术完成该预测。 LZA算法分为精确和不精确的类别。大多数现有算法本质上是不精确的，这预测了换档量，具有1位的可能误差。因此，这些不精确的LZA算法需要错误检测电路。本文提出了一种与加法器并行实现的错误检测逻辑，并使用LZA的零件硬件，导致在与通用LZA和误差相比时，分别将区域和功耗降低35％-39％和44％-48％检测电路。

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