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Automatic Translation of Software Binaries onto FPGAs

机译：将软件二进制文件自动翻译在FPGA上

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The introduction of advanced FPGA architectures, with built-in DSP support, has given DSP designers a new hardware alternative. By exploiting its inherent parallelism, it is expected that FPGAs can outperform DSP processors. This paper describes the process and considerations for automatically translating binaries targeted for general DSP processors into Register Transfer Level (RTL) VHDL or Verilog code to be mapped onto commercial FPGAs. The Texas Instruments C6000 DSP processor architecture is chosen as the DSP processor platform, and the Xilinx Virtex II as a target FPGA. Various optimizations are discussed, including data dependency analysis, procedure extraction, induction variable analysis, memory optimizations, and scheduling. Experimental results on resource usage and performance are shown for ten software binary benchmarks. Results show performance gains of 3-20X in the FPGA designs over that of the DSP processors in terms of reductions of execution cycles.
机译：具有内置DSP支持的先进FPGA架构引入，具有DSP设计人员新的硬件替代品。通过利用其固有的并行性，预计FPGA可以优于DSP处理器。本文介绍了将常规DSP处理器自动转换为寄存器传输级别（RTL）VHDL或Verilog代码的过程和注意事项，以映射到商业FPGA上。德州仪器C6000 DSP处理器架构被选为DSP处理器平台，Xilinx Virtex II作为目标FPGA。讨论了各种优化，包括数据依赖性分析，过程提取，归纳可变分析，内存优化和调度。关于资源使用和性能的实验结果显示为十个软件二进制基准。结果在执行循环的减少方面，FPGA在FPGA处理器中的3-20倍的性能增益显示为3-20倍。

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