In this paper a novel technique is illustrated to implement fault-tolerant circuits. On-line testing is used to detect errors and a reconfiguration technique is applied to by-pass the erroneous unit. The main characteristics of this technique are the reduced power dissipation compared to formal implementations and the minimum required time to perform the reconfiguration process. Application of this technique on FIRs is illustrated and a maximum of 40% is saved from the area required for integration, while a 33% of power reduction is achieved.
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