VLSI IMPLEMENTATION OF VERY LOW-POWER MOTION ESTIMATOR FOR SCALEABLE CODING SYSTEMS

机译：用于可扩展编码系统的非常低功率运动估算器的VLSI实现

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Currently, various video formats, such as QCIF, GIF, CCIR601 and HDTV, are widely used in the world. Since their resolution is different, the processing speed required is different for motion estimation. Hence we need to design the specific hardware architecture for each format. In this study, we propose a flexible motion estimator to meet the processing speed of all formats with a common architecture, wherein there are four searching algorithms built to satisfy the various processing-time required. For applying to low-power systems, the computational kernel employs four processing-elements in this chip. With timing mode control, the throughput rate of the proposed motion estimator can achieve from 3k to 180k blocks to meet different applications while this chip works on 50MHz. The total gate count is less than 5k and the power dissipation is no more than 0.1mW in the worst case. Hence the very low-power motion estimation is appropriate for portable systems.

机译：目前，各种视频格式，例如QCIF，GIF，CCIR601和HDTV，广泛应用于世界。由于它们的分辨率不同，所需的处理速度是不同的运动估计。因此，我们需要为每种格式设计特定的硬件架构。在本研究中，我们提出了一种灵活的运动估计器，以满足所有格式的处理速度，其中具有共同的架构，其中有四个搜索算法以满足所需的各种处理时间。为了应用于低功耗系统，计算内核在该芯片中采用四个处理元件。通过定时模式控制，所提出的运动估计器的吞吐率可以从3K到180k块实现，以满足不同的应用，而该芯片工作在50MHz上。总栅极计数小于5K，最坏情况下功耗不超过0.1MW。因此，非常低功率的运动估计适用于便携式系统。

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《IEEE International Workshop on System-on-Chip for Real-Time Applications》|2003年||共4页
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Shih-Chang Hsia;
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VLSI IMPLEMENTATION OF VERY LOW-POWER MOTION ESTIMATOR FOR SCALEABLE CODING SYSTEMS

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