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Reallocation and Rescheduling after Floor-planning for Timing Optimization

机译：定时优化落地规划后重新分配和重新安排

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As the dimension of integrated circuits proceeds into deep sub-micron level, interconnect delay is playing a dominant role In total delay of a circuit The result of high-level synthesis is often violated by interconnect-delay in physical design phase, especially in timing aspect. Reallocation and Rescheduling after floor-plan can be very helpful to the delay optimization of physical design. A force-balance based interconnect-delay driven algorithm for reallocation and rescheduling (FIBER) is presented in this paper. The delay of interconnect wire is specially attended in this algorithm. In this algorithm, a reallocation process is first engaged after floor-planning, in order to erase those data-paths which do not satisfy the timing constraint A rescheduling process will be engaged if this reallocation process is not successfully finished. A HLS system, TUSYN, is also presented as the background knowledge of the algorithm.
机译：随着集成电路的尺寸进入深层微米级，互连延迟在电路的总延迟中播放主导作用，高级合成的结果通常通过物理设计阶段的互连延迟而违反，尤其是在时序方面。在落地计划后重新分配和重新安排对物理设计的延迟优化非常有帮助。本文介绍了一种用于重新分配和重新安排（光纤）的力平衡的互连延迟驱动算法。该算法专门参加互连线的延迟。在该算法中，首先在落地计划之后首先接合重新定位过程，以擦除那些不满足时序约束的数据路径，如果该重新定位过程未成功完成，则在重新安排过程将接合重新安排过程。 HLS系统Tusyn也被呈现为算法的背景知识。

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