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首页> 外文会议>International Symposium on Power Semiconductor Devices and ICs >A Marvelous Low on-reslstance 20V rated Self Alignment Trench MOSFET (SAT-MOS) in a 0.35μm LSI design rule with both high forward blocking voltage yield and large current capability
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A Marvelous Low on-reslstance 20V rated Self Alignment Trench MOSFET (SAT-MOS) in a 0.35μm LSI design rule with both high forward blocking voltage yield and large current capability

机译：一个奇妙的低折叠20V额定自对准沟槽MOSFET（SAT-MOS）在0.35μm的LSI设计规则中，具有高前锋阻塞电压产量和电流能力大

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In this paper, we propose the SAT-MOS, which achieved marvelous performance of the Specific on-resistance (Ron, sp): 6.5mΩmm{sup}2 (@Vdss=30.8V) by minimizing the unit cell pitch but not too small (Fig.4) on a 0.35μm LSI design rule. This is the lowest value of 20V rated MOSFETs ever been reported. The fabricated SAT-MOS 's Ron,sp ratio to the Si limit reaches the ultimate value 2)8% in this voltage class (Fig.l). An yield of a forward blocking voltage characteristics (Vdss) is so sensitive for the uniformity of the shallow source trench depth on a large size wafer to maintain as acceptable value for the mass-production without any special care to obtain an N and P common contact in a shallow p-base region accurately. We could solve this trade-off problem between minimizing a unit cell to reduce a Ron and a Vdss yield stability in a"Dual trench process" on the 0.35μm fine design rule by optimizing the Self-Alignment shallow trench Contact (SAC) ion implantation. So, the SAT-MOS maintains an excellent Vdss uniformity on a wafer, because our proposed SAC structure and procedure has a very large process window for SAC trench depth if the source contact trench depth disperses more than 20%. As a result, we could present the SAT-MOS, which has both a large current capability of over 100A/mm{sup}2 in a static forward bias condition and an avalanche ruggedness of over 25A/mm{sup}2 during undamped inductive switching (UTS).
机译：在本文中，我们提出了SAT-MOS，通过最大限度地减少单位细胞间距但不太小，实现了SAT-MOS的特定导通电阻（RON，SP）：6.5mΩmm{sup} 2（@ vdss = 30.8v）的奇妙性能。 （图4）在0.35μm的LSI设计规则上。这是迄今为止的20V级MOSFET的最低值。制造的SAT-MOS的RON，SP比与SI极限达到该电压类（图1）中的终极值2）。正向阻断电压特性（Vdss）的产量对于大尺寸晶片上的浅源沟槽深度的均匀性如此敏感，以保持批量生产的可接受的值，而无需任何特殊的注意，以获得n和p comance接触在浅水区精确地区。通过优化自对准浅沟触头（SAC）离子植入，最小化单元电池在最小化单位单元以减少一个单位单元以减少ron和Vdss的稳定性之间的权衡问题，在0.35μm微型设计规则上的“双沟程过程”中产生稳定性。因此，SAT-MOS在晶圆上保持优异的VDSS均匀性，因为我们所提出的SAC结构和程序具有非常大的过程窗口，如果源接触沟槽深度分散超过20％，则具有非常大的囊沟深度。结果，我们可以呈现SAT-MOS，其在静态正向偏置条件下具有超过100A / mm {SUP} 2的大电流能力，以及在透明电感期间超过25a / mm {sup} 2的雪崩坚固性切换（UTS）。

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