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首页> 外文会议>IEEE International Symposium on Parallel and Distributed Processing >FeatureVerilog: Extending Verilog to support Feature-Oriented Programming
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FeatureVerilog: Extending Verilog to support Feature-Oriented Programming

机译：Featureverilog：扩展Verilog以支持面向功能的编程

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Nowadays, systems are getting harder and harder to develop and maintain. For a long time, researchers have tried to solve these problems by increasing the level of abstraction, but RTL description languages (e.g. Verilog) are still being widely used. This paper proposes FeatureVerilog, a novel hardware description language that extends Verilog to support Feature-Oriented Programming (FOP). FeatureVerilog does not avoid the detailed description of RTL, but it can organize it in a more reasonable way. We have implemented a prototype pre-compiler for FeatureVerilog and used it to re-develop the OpenRISC 1200 project. The comparison of our implementation and the original one shows that FeatureVerilog can eliminate the duplicate code in the latter implementation effectively.
机译：如今，系统越来越难以开发和维护。长期以来，研究人员通过增加抽象水平来解决这些问题，但RTL描述语言（例如Verilog）仍然被广泛使用。本文提出了Featureverilog，这是一种新的硬件描述语言，它扩展了Verilog来支持面向功能的编程（FOP）。 Featureverilog不避免RTL的详细描述，但它可以以更合理的方式组织它。我们已经为Featureverilog实现了一个原型编译器，并使用它来重新开发OpenRisc 1200项目。我们的实现和原始的比较显示Featureverilog可以有效地消除后者实现中的重复代码。

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