PIM architectures to support petaflops level computation in the HTMT machine

机译：PIM架构为了支持HTMT机器的Petaflops级别计算

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The HTMT project is an ambitions attempt to combine a variety of emerging technologies into a petaflops-level computing system available many years before an equivalent machine can be built from current technologies. One of the key problems in such an architecture is overcoming latencies between the main memory and the high performance CPUs, which can grow to literally tens of thousands of cycles. In HTMT the approach taken to overcoming this is a multi-level memory system, with most of the levels to be fabricated using Processing-In-Memory (PIM) technologies in architectures which actively manage the flow of data without centralized CPU control. This paper overviews the current architecture for such chips within the context of the HTMT system, and how this architecture supports the expected execution model.

机译：HTMT项目是一项雄心壮志，试图将各种新兴技术与在当前技术中的等效机器之外的Petaflops-Level计算系统中相结合。这种架构中的关键问题之一是克服主存储器和高性能CPU之间的延迟，这可以生长为数万个周期。在HTMT中，克服这一点的方法是一个多级存储系统，其中大多数级别都使用架构中的内存（PIM）技术在没有集中式CPU控制的情况下主动管理数据流。本文在HTMT系统的上下文中概述了此类芯片的当前架构，以及该体系结构如何支持预期的执行模型。

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《International Workshop Innovative Architecture for Future Generation High-Performance Processors and Systems》|2000年||共10页
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Kogge P.M.; Brockman J.b.; Institute of Electric and Electronic Engineer;
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中图分类自动化技术、计算机技术;
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PIM architectures to support petaflops level computation in the HTMT machine

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