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首页> 外文会议>International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications >Crosstalk on Sampling Clock and Additive Dither in Radio Receiver IF Digitization
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Crosstalk on Sampling Clock and Additive Dither in Radio Receiver IF Digitization

机译：在无线电接收机中采样时钟和附加抖动的串扰如果数字化

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摘要

Radio receiver intermediate frequency digitization generally requires high resolution of analog-to-digital conversion with wide bandwidth. The sampling clock performance is a key concern and is widely investigated in the published literatures. However, most of the issues mainly focused on the clock jitter with white Gaussian noise only. This paper present a more realistic analog-to-digital conversion analysis model based on the actual circuit noise conditions, particularly investigating on the clock jitter error with the combination of Gauss distribution noise and circuit noise (interference). An analytical expression for the A/D conversion with the combined clock jitter error is developed. The computer simulations are presented, which showed excellent agreement with the developed expression. Also, a solution of additive dithering technique is present to reduce the effect of circuit crosstalk on sampling clock.
机译：无线电接收器中频数字化通常需要高分辨率的模数转换，具有宽带宽度。采样时钟性能是关键问题，在发布的文献中被广泛调查。然而，大多数问题主要集中在时钟抖动上仅具有白色高斯噪声。本文提出了一种基于实际电路噪声条件的现实模数转换分析模型，特别是在时钟抖动误差与高斯分配噪声和电路噪声（干扰）的组合研究。开发了使用组合时钟抖动误差的A / D转换的分析表达式。提出了计算机模拟，显示出与发达的表达式吻合很好。而且，存在一种添加剂抖动技术的解决方案以减少电路串扰对采样时钟的影响。

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