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首页> 外文会议>International Conference on Electronic Design and Signal processing >A HARDWARE MODEL FOR FULL SEARCH BLOCK MATCHING ALGORITHM IN VIDEO ENCODING FOR MOTION ESTIMATION
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A HARDWARE MODEL FOR FULL SEARCH BLOCK MATCHING ALGORITHM IN VIDEO ENCODING FOR MOTION ESTIMATION

机译：用于运动估计视频编码中全搜索块匹配算法的硬件模型

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摘要

Today's technological growth in the semiconductor industry has created unprecedented demand for electronic gadgets that are very sophisticated and user friendly. Interfaces with audio/video capabilities have further enhanced the demand for the products in the market. Video data needs to be compressed before storage and transmission. Complex algorithms are required to eliminate the redundancy. Extracting the redundant information and compressing video sequences require high speed power efficient architectures. In this paper, Full Search Block Matching Algorithm (FSBMA) for motion estimation and compensation uses 2-dimensional systolic array architectures. The blocks of the architecture are processing element, shift register arrays, address generators for search area value, reference block value, enable signal generator, candidate region monitor and best match selection unit. The system has single clock and reset. The designed system has an image resolution of 176x144 and works at a frequency of 45.792MHz. It takes serial inputs and performs parallel processing to reduce IO pin counts. All the blocks and the top module have been designed. The FSBMA has been modeled in Verilog Hardware Description Language and simulated against its functional specifications.
机译：今天，半导体行业的技术增长为非常复杂和用户友好的电子小工具创造了前所未有的需求。具有音频/视频功能的接口进一步提高了对市场产品的需求。视频数据需要在存储和传输之前压缩。需要复杂的算法来消除冗余。提取冗余信息和压缩视频序列需要高速功率有效的架构。在本文中，用于运动估计和补偿的完整搜索块匹配算法（FSBMA）使用二维收缩阵列架构。架构的块是处理元件，移位寄存器阵列，用于搜索区域值的地址生成器，参考块值，使能信号发生器，候选区域监视器和最佳匹配选择单元。系统具有单个时钟并重置。设计的系统具有176x144的图像分辨率，并以45.792MHz的频率工作。它需要串行输入并执行并行处理以减少IO引脚计数。所有块和顶部模块都已设计。 FSBMA已在Verilog硬件描述语言中进行建模并模拟其功能规范。

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