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An ESL Methodology for Rapid Creation of Embedded Aerospace Systems using Hardware-Software Co-Design on Virtual Platforms

机译：用于在虚拟平台上使用硬件 - 软件共同设计的嵌入式航空航天系统快速创建嵌入式航空航天系统的ESL方法

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This paper presents an Electronic System-Level (ESL) methodology and framework for the system specification, design space exploration, performance analysis, and hardware/software implementation of aerospace electronic systems subject to Quality of Results (QoR) constraints such as execution time, communication rate, technology, as well as Size, Weight and Power (SWaP). In particular, we show how SWaP constraints could be converted into bounds on the target hardware platform, how several potential architectures could be devised for the system, how each potential architecture and mapping could be evaluated for performance, hardware resource usage and power taking into account the impact of Triple Modular Redundancy (TMR), and how a selected architecture could be exported as a hardware/software Register-Transfer Level (RTL) implementation. This methodology is enabled by (and demonstrated with) the SpaceStudio tool suite, a complete HW/SW co-design platform with the unique ability to transform functions between hardware and software as designers decide on the makeup of their system. The methodology and each of its steps are demonstrated on a video Motion-JPEG (M-JPEG) decoder example. 11 different architectures of the M-JPEG were quickly specified and evaluated this way. These architectures used 0 to 5 MicroBlaze or LEON soft-core processors, used CoreConnect or AMBA bus architectures, ran with either bare-metal embedded software or the uCOS/II Real-Time Operating System (RTOS), and differed in their hardware/software partitioning of application tasks. The M-JPEG decoder was also realized on a commercial equivalent of a Virtex-4 radiation-hardened FPGA and results showed that high-level estimates of performance and hardware resource usage were respectively within 15.5% and 17.6% of the final implementation.
机译：本文提出了一种电子系统级（ESL）方法和系统规范，设计空间探索，性能分析和硬件/软件实现的电子系统级（ESL）方法和框架，其经受结果（QOR）约束的质量（如执行时间，通信）速率，技术，尺寸，重量和功率（交换）。特别是，我们展示了转换约束如何转换为目标硬件平台上的界限，如何为系统设计了几种潜在架构，如何评估每个潜在的架构和映射，以考虑性能，硬件资源使用和电力三重模块化冗余（TMR）的影响以及如何将所选架构导出为硬件/软件寄存器传输级别（RTL）实现。该方法由Spacestudio Tool Suite，一个完整的HW / SW Co-Design平台启用（和演示），具有独特的能力在设计人员决定其系统的构成时，具有独特的硬件和软件之间的功能。在视频Motion-JPEG（M-JPEG）解码器示例上展示了方法和每个步骤。 11以这种方式快速指定和评估M-JPEG的不同架构。这些架构使用0到5微卷发或莱昂软核处理器，使用Coreconnect或Amba总线架构，并使用裸机嵌入式软件或UCOS / II实时操作系统（RTOS）进行，并且在其硬件/软件中不同申请任务的分区。 M-JPEG解码器还以商业等价物于商业等效于Virtex-4辐射硬化的FPGA实现，结果表明，性能和硬件资源的高级别估计分别在最终实施的15.5％和17.6％之内。

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