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首页> 外文会议>International Conference on Materials Engineering and Science >Effect of substrate thickness on coating roughness Ti/AlTiN during interaction process Parameter
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Effect of substrate thickness on coating roughness Ti/AlTiN during interaction process Parameter

机译：衬底厚度对涂层粗糙度Ti / Altin的影响互动过程参数

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Ti/TiAlN coatings were deposited on tungsten carbide substrates and consist of the target Ti0.5A10.5 using sputtering system is one of the main techniques which done be coating substrate. This research aimed is to develop the model a PVD magnetron sputtering process that can predict the relationship between process input parameters and the resulting coating properties and performance. RSM Response Surface Methodology was used, one of the most cost-effective and practical techniques to develop the process model. The influence of substrate thickness on the structural properties of the coatings was investigated and the effect of bias voltage on the microstructure was investigated. The number of crystallite grain size reduced with the increase of the bias voltage then reduce minimum roughness 0.07157 (μm) and became maximum roughness 0.7856 (μm). The crystalline grain size of the coatings increased as the bias voltage was raised from 50 to 75 V, and then decreased with further increase of the bias voltage.
机译：Ti / TiAlN涂层沉积在碳化钨基材上，并由溅射系统由靶Ti0.5a10.5组成的是完成是涂覆基材的主要技术之一。旨在开发模型A PVD磁控溅射过程，可以预测过程输入参数与所得涂层性能和性能之间的关系。使用RSM响应曲面方法，是开发过程模型的最具成本效益和实用的技术之一。研究了基板厚度对涂层结构性质的影响，并研究了偏置电压对微结构的影响。随着偏置电压的增加，晶体晶粒尺寸的数量随后减小最小粗糙度0.07157（μm），变为最大粗糙度0.7856（μm）。随着偏置电压升高50至75V，涂层的晶粒尺寸增加，然后随着偏置电压的进一步增加而降低。

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