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首页> 外文会议>ICGCE 2013 >IMPLEMENTATION OF EXTENDED OPEN CORE PROTOCOL INTERFACE MEMORY SYSTEM USING Verilog HDL
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IMPLEMENTATION OF EXTENDED OPEN CORE PROTOCOL INTERFACE MEMORY SYSTEM USING Verilog HDL

机译：使用Verilog HDL实现扩展开放核心协议接口内存系统

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摘要

In today's Soc design, a large number of Intellectual Property(IP) are incorporated and their complexity keeps increasing depending upon the application. Hence for communication between these IP cores, a standard communication protocol for all the IP entities in the IC is developed ,the Open Core Protocol(OCP), instead of communicating for each set of IP cores. Open Core Protocol (OCP) achieves the goal of IP design reuse and meets shorter time to market requirements when compared to the standard bus interfaces. OCP comes under the class of Socket based interface standard. This paper mainly focuses on the design and implementation of a memory interfacing system using Extended OCP signals along with burst support. The design mainly includes Processor as master and RAM as slave. Here we perform the communication (simple read and write operations) between the two entities using OCP architecture with various modes burst support and the newly added set of signals from the class of simple extensions and dataflow signals. The main advantage of adding these signals is to ensure the correctness of send and receive data because our aim is to make the communication protocol secure and efficient. Also the importance of read/write command extension Read Exclusive operation is implemented. The proposed design is implemented in Verilog HDL and synthesis is done using Xilinx ISE Design Suite 12.1.Finally power calculations were taken using Xilinx Xpower Analyser.
机译：在当今的SoC设计中，纳入了大量的知识产权（IP），并且它们的复杂性因应用而不断增加。因此，对于这些IP核心之间的通信，开发了IC中所有IP实体的标准通信协议，开放核心协议（OCP），而不是为每组IP核心进行通信。打开核心协议（OCP）与标准总线接口相比，达到IP设计重用的目标，并满足较短的市场需求。 OCP来自基于套接字的界面标准。本文主要侧重于使用扩展OCP信号以及突发支持的内存接口系统的设计和实现。该设计主要包括作为从属掌握和RAM作为从属的处理器。在这里，我们使用具有各种模式突发支持的OCP架构和来自简单扩展的类的新添加信号集之间执行通信（简单读写操作）。添加这些信号的主要优点是确保发送和接收数据的正确性，因为我们的目标是使通信协议安全和高效。还实现了读/写命令扩展名读取独占操作的重要性。所提出的设计是在Verilog HDL和合成中实现的，使用Xilinx ISE设计套件12.1。使用Xilinx XPower分析仪采取初始功率计算。

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