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首页> 外文会议>IFIP World Computer Congress TC10 Working Conference on Distributed and Parallel Embedded Systems >VERIFICATION FRAMEWORK FOR UML - BASED DESIGN OF EMBEDDED SYSTEMS
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VERIFICATION FRAMEWORK FOR UML - BASED DESIGN OF EMBEDDED SYSTEMS

机译：基于UML的嵌入式系统设计验证框架

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摘要

System level design incorporating system modeling and formal specification in combination with formal verification can substantially contribute to the correctness and quality of the embedded systems and consequently help reduce the development costs. Ensuring the correctness of the designed system is, of course, a crucial design criterion especially when complex distributed (realtime) embedded systems are considered. Therefore, this paper aims at presenting a verification framework designated for formal verification and validation of UML-based design of embedded systems. It first introduces an approach of using the AsmL language for acquiring formal models of the UML semantics and consequently presents an on-the-fly model checking technique designed to run the formal verification directly over those semantic models.
机译：系统级设计结合正式验证的系统建模和正式规范可以基本上有助于嵌入式系统的正确性和质量，从而有助于降低开发成本。 当然，确保设计系统的正确性是关键设计标准，特别是当考虑复杂的分布式（实时）嵌入式系统时。 因此，本文旨在提出指定的验证框架，以进行正式验证和验证基于UML的嵌入式系统的设计。 它首先介绍了使用ASML语言获取UML语义的正式模型的方法，从而提出了一种在飞行模型检查技术，旨在直接在这些语义模型上运行正式验证。

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