Heterogeneous integration (HI) offers a path to increase bandwidth density and reducing power consumption per area for advanced microelectronic systems by minimizing fan-in/out structures and reducing parasitics. To achieve state-of-the-art areal bandwidth density, 3D HI is required with through silicon vias (TSVs) with extremely tight interconnect pitches (< 50 μm) and high aspect ratios. Fabrication and fill of these proposed TSVs pose significant challenges including substrate thinning, high aspect ratio deep reactive ion etching (DRIE), conformal thin film deposition to deposit insulating layers as well as seed metals for electrodeposition, and void-free fill of the TSVs. Here, we target an interconnect pitch of 20 μm and TSV diameter of 5 μm. At these dimensions, DRIE lag limits the TSV depth to 100 μm. The TSVs are integrated using a via-last scheme with atomic layer deposition (ALD) Al_2O_3 as the insulating liner and ALD Pt serving as both the barrier and electrochemical deposition (ECD) seed liner. In this work, we describe the integration scheme for these high density TSVs and focus on the ECD process for achieving a void-free fill with Cu as well as characterization approaches using focus ion beam (FIB) cross sectioning.
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