• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>International Electron Devices Meeting >COB stack DRAM cell technology beyond 100nm technology node (invited paper)
【24h】

COB stack DRAM cell technology beyond 100nm technology node (invited paper)

机译：COB堆栈DRAM Cell技术超出100nm技术节点（邀请纸）

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Recent successful development of sub-0.15 μm DRAM technology gives bright future for DRAMs. [1～4] However, as the DRAM technology approaches to 100 tun technology node and beyond, key performance parameters such as read/write speed and data retention time become much seriously limited by memory cell itself rather than others such as core control circuit and periphery circuit. In these regimes, memory cell performance is strongly influenced by its parasitic resistance and parasitic capacitance which might overwhelm the performances of active device of array transistor and memory cell capacitor. Furthermore, strong demand of high performance with low power consumption drives memory cell toward high performance array transistor, low parasitic bit line capacitance and low parasitic resistance. In this paper, we systematically investigated the key issues of COB stack cell technology for future DRAM, and proposed the most possible solutions for those issues in 6 key process areas such as isolation, array transistor and word line, 1st landing pad, bit line, 2nd landing pad, and capacitor process.
机译：近期0.15微米DRAM技术的最近成功发展为DRAM提供了光明的未来。然而，随着DRAM技术接近100个TUN技术节点和超越，诸如读/写速度和数据保留时间之类的关键性能参数因存储器单元而不是诸如核心控制电路等其他人而受到严重限制的外围电路。在这些制度中，记忆单元性能受其寄生电阻和寄生电容的强烈影响，这可能压倒阵列晶体管和存储器电池电容器的主动装置的性能。此外，利用低功耗的高性能需求强大，将存储器电池驱动到高性能阵列晶体管，低寄生位线电容和低寄生电阻。在本文中，我们系统地调查了COB堆栈单元技术的关键问题，为未来的DRAM，并为6个关键过程领域提出了最可能的解决方案，例如隔离，阵列晶体管和字线，第一升降垫，位线，第二升降垫和电容器工艺。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号