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SIMULATION AND OPTIMIZATION OF VLSI INTERCONNECTS IN PRINTED CIRCUIT BOARDS

机译:打印电路板上VLSI互连的仿真和优化

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Interconnects in high-speed VLSI circuits and systems exhibit transmission line effects. With subnanosecond rise time, signals through the interconnects in printed circuit boards (PCB) suffer from delay, distortion, reflection, and crosstalk. Such signal integrity aspects are important factors in the electrical design of printed circuit boards. In this paper, we outline efficient techniques recently developed for addressing two specific aspects of the high-speed interconnect problem, namely, simulation and performance optimization. These techniques accommodate distributed interconnect models represented by lossy coupled transmission lines.
机译:高速VLSI电路和系统中的互连表现出传输线效应。在亚纳秒的上升时间内,通过印刷电路板(PCB)互连的信号会受到延迟,失真,反射和串扰的影响。这种信号完整性方面是印刷电路板电气设计中的重要因素。在本文中,我们概述了最近开发的用于解决高速互连问题的两个特定方面的有效技术,即仿真和性能优化。这些技术适应以有损耦合传输线为代表的分布式互连模型。

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