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首页> 外文会议>Microelectronics Technology and Devices-SBMicro 2008 >DC performance and Low Frequency Noise in n-MOSFETs using Self-Aligned Poly-Si/SiGe Gate
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DC performance and Low Frequency Noise in n-MOSFETs using Self-Aligned Poly-Si/SiGe Gate

机译：使用自对准多晶硅/ SiGe栅极的n-MOSFET的直流性能和低频噪声

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摘要

The characterization of an n-MOS transistor with poly-Si/SiGe Gate fabricated with the CMOS process entirely developed in the Center for Semiconductor Components (CCS) at UNICAMP is presented. The Gate layer was grown by vertical LPCVD at 800 ℃. The resultant transistor has a channel region with oxide thickness of 30 nm and self-aligned thick S/D region. The DC and G_m characteristics of poly-Si/SiGe n-MOS transistor are reported. The turn-on in the I-V characteristics increases and at a drain-to-source bias V_(DS) of +0.1 V nMOSFETs with 3 μm gate length had peak transconductance (μS) increased as well, compared with conventional n-MOS with poly-Si gate. The G_m characteristics and low frequency noise 1/f of the n-MOS transistors are studied using devices sizes with width of 20 nm and several lengths. Promising devices for RF and microwave circuit applications, show low 1/f and high values of transconductance.
机译：展示了在UNICAMP的半导体组件中心（CCS）完全开发的，采用CMOS工艺制造的带有多晶硅/ SiGe栅极的n-MOS晶体管的特性。栅极层是通过垂直LPCVD在800℃下生长的。所得晶体管具有氧化膜厚度为30nm的沟道区和自对准的厚S / D区。报告了多晶硅/ SiGe n-MOS晶体管的DC和G_m特性。与具有多晶硅的传统n-MOS相比，IV特性的导通增加，并且漏极至源极偏置V_（DS）为+0.1 V，栅极长度为3μm的nMOSFET的峰值跨导（μS）也增加了-硅门。 n-MOS晶体管的G_m特性和低频噪声1 / f使用宽度为20 nm且长度为数个长度的器件进行研究。用于射频和微波电路应用的有前途的器件显示出低的1 / f和高的跨导值。

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  • 来源
  • 会议地点 Gramado(BR);Gramado(BR);Gramado(BR);Gramado(BR);Gramado(BR);Gramado(BR)
  • 作者

    H.G.Jimenez; L.T. Manera; R.C. Teixeira; M. F. Rautemberg; J. A. Diniz; I. Doi; P. J. Tatsch; H.E.Figueroa; J. W. Swart;

  • 作者单位

    Center for Semiconductor Components, P.O Box 6061 University of Campinas - UNICAMP, 13083-970, Campinas-SP, Brazil;

    Center for Semiconductor Components, P.O Box 6061 University of Campinas - UNICAMP, 13083-970, Campinas-SP, Brazil;

    Center for Semiconductor Components, P.O Box 6061 University of Campinas - UNICAMP, 13083-970, Campinas-SP, Brazil;

    Center for Semiconductor Components, P.O Box 6061 University of Campinas - UNICAMP, 13083-970, Campinas-SP, Brazil;

    Center for Semiconductor Components, P.O Box 6061 University of Campinas - UNICAMP, 13083-970, Campinas-SP, Brazil;

    Center for Semiconductor Components, P.O Box 6061 University of Campinas - UNICAMP, 13083-970, Campinas-SP, Brazil;

    Center for Semiconductor Components, P.O Box 6061 University of Campinas - UNICAMP, 13083-970, Campinas-SP, Br;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 微电子学、集成电路（IC）;
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