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首页> 外文会议>Microelectronics technology and devices - SBMicro 2010 >Three-Dimensional Simulation of Biaxially Strained Triple-Gate FinFETs: A Method to Compute the Fin Width and Channel Length Dependences on Device Electrical Characteristics
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Three-Dimensional Simulation of Biaxially Strained Triple-Gate FinFETs: A Method to Compute the Fin Width and Channel Length Dependences on Device Electrical Characteristics

机译：双轴应变三栅极FinFET的三维仿真：一种计算鳍宽和沟道长度对器件电气特性的依赖性的方法

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摘要

Multiple gate devices have been considered as an alternative to the miniaturization owing to the better electrostatic control, leading to the short channel effects reduction (1). These devices also provide an increase in the drain current due to the formation of multiple inversion layers, when compared to a planar single gate transistor (1). Triple gate FinFETs are made on a thin and tall layer of silicon surrounded by the gate electrode over the buried oxide and its schematic view is presented at Figure 1. The inversion layers are formed at the sidewalls and the top. However, the carrier mobility depends on the crystallographic orientation. The electron mobility in the surface (100), which is the most common surface for the top gate, is higher than in the surface (110), commonly the sidewall gates (2).
机译：由于更好的静电控制，多栅极器件已被认为是小型化的替代方案，从而减少了短沟道效应（1）。与平面单栅晶体管（1）相比，由于形成多个反型层，这些器件还提供了漏极电流的增加。三栅极FinFET在被掩埋的氧化物上方的栅电极包围的薄而高的硅层上制成，其示意图如图1所示。在侧壁和顶部形成了反转层。然而，载流子迁移率取决于晶体学取向。表面（100）是顶栅最常见的表面，其电子迁移率高于表面（110），通常是侧壁栅（2）的电子迁移率。

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  • 来源
  • 会议地点 Sao Paulo(BR);Sao Paulo(BR)
  • 作者

    Renan Trevisoli Doria; Marcelo Antonio Pavanello;

  • 作者单位

    LSI/PSI/USP, University of Sao Paulo, Av. Prof. Luciano Gualberto, trav. 3, n. 158,05508-900, Sao Paulo, Brazil;

    LSI/PSI/USP, University of Sao Paulo, Av. Prof. Luciano Gualberto, trav. 3, n. 158,05508-900, Sao Paulo, Brazil rnDepartment of Electrical Engineering, Centro Universitario da FE1,Av. Humberto de Alencar Castelo Branco 3972,09850-901, Sao Bernardo do Campo, Brazil;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 半导体技术;
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