Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders

机译：使用有符号数字加法器的时间交错多相抽取滤波器

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Decimation filters for high-speed oversampling DeltaSigma converters have been investigated by using signed-digit adders. Time-interleaved technique is introduced to a polyphase FIR filter to overcome operation speed limitation due to the setup and hold time constraint for delayed flip-flops. It is found that in this architecture, the adder tree based on ternary signed-digit full adders effectively improves the operation speed. A third-order filters with a decimation factor of 8 is designed by assuming a 0.18-mum standard CMOS technology. Signal-level simulation shows that the operation frequency of the present time-interleaved filter is improved by 20% compared with conventional polyphase filters.

机译：通过使用带符号数字加法器，对用于高速过采样DeltaSigma转换器的抽取滤波器进行了研究。时间交错技术被引入多相FIR滤波器中，以克服由于延迟触发器的建立和保持时间限制而导致的操作速度限制。发现在该架构中，基于三进制有符号位全加器的加法器树有效地提高了运算速度。通过采用0.18um标准CMOS技术设计了抽取因子为8的三阶滤波器。信号级仿真表明，与传统的多相滤波器相比，本发明的时间交错滤波器的工作频率提高了20％。

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来源
《Multiple-Valued Logic, 2009. ISMVL '09》|2009年|245-249|共5页
会议地点 Naha(JP);Naha(JP)
作者
Murozuka M.; Ikeura K.; Adachi F.; Machida K.; Waho T.;
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Dept. of Electr. Electron. Eng., Sophia Univ., Tokyo;

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CMOS digital integrated circuits; FIR filters; adders; flip-flops; sigma-delta modulation; signal sampling; CMOS technology; delayed flip-flop; high-speed oversampling delta-sigma converter; hold time constraint; polyphase FIR filter; size 0.18 mum; ternary signed-digit full adder tree; third-order filter; time-interleaved polyphase decimation filter; decimation filter; delta-sigma modulator; multiple-valued; signed-digit;

机译：CMOS数字集成电路; FIR滤波器;加法器;触发器; sigma-delta调制;信号采样; CMOS技术;延迟触发器;高速过采样delta-sigma转换器;保持时间限制;多相FIR滤波器;尺寸0.18微米三进制有符号全加法树;三阶滤波器;时间交织的多相抽取滤波器;抽取滤波器; delta-sigma调制器;多值;有符号数字;

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专利

1. 3-D IIR filtering using decimated DFT-polyphase filter bank structures [J] . Kuenzle B., Bruton L.T. IEEE transactions on circuits and systems . I , Regular papers . 2006,第2期

机译：使用抽取DFT多相滤波器组结构的3-D IIR滤波
2. 3-D IIR Filtering Using Decimated DFT-Polyphase Filter Bank Structures [J] . B. Kuenzle, Len T. Bruton IEEE Transactions on Circuits and Systems. I, Regular Papers . 2006,第2期

机译：使用抽取DFT多相滤波器组结构的3D IIR滤波
3. On the Polyphase Decomposition for Design of Generalized Comb Decimation Filters [J] . Laddomada M. IEEE transactions on circuits and systems . I , Regular papers . 2008,第8期

机译：广义梳状抽取滤波器设计的多相分解
4. Time-interleaved polyphase decimation filter using signed-digit adders [C] . Masaki Murozuka, Kazumasa Ikeura, Fumiyuki Adachi, IEEE International Symposium on Multiple-Valued Logic . 2009

机译：使用符号位添加剂的时间交错多相抽取滤波器
5. Three-dimensional IIR filtering using decimated DFT-polyphase filter bank structures. [D] . Kuenzle, Bernhard. 2005

机译：使用抽取DFT多相滤波器组结构的三维IIR滤波。
6. Optimal Sharpening of Compensated Comb Decimation Filters: Analysis and Design [O] . David Ernesto Troncoso Romero, Massimiliano Laddomada, Gordana Jovanovic Dolecek -1

机译：补偿梳状抽取滤波器的最佳锐化：分析和设计
7. Low complexity all-pass based polyphase decimation filters for ECG monitoring [O] . Yaprak Eminaga, Adem Coskun, Sterghios A. Moschos, 2015

机译：基于低复杂性的Poly-Pass PolyPhiee Divimation滤波器，用于ECG监控

Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders

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