首页> 外文会议>Multiple-Valued Logic, 2009. ISMVL '09 >Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

【24h】

Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

机译：分层临时存储器作为软计算平台的评估及其VLSI架构

获取原文

页面导航

摘要
著录项
相似文献
相关主题

摘要

A large number of real world applications, like user support systems, can still not be performed easily by conventional algorithms in comparison with the human brain. Recently, such intelligence has often been reached by using probability based systems. This paper presents results on the implementation of one such user support system, namely an intention estimation information appliance system, on a Bayesian network as well as hierarchical temporal memory. The latter is a new and quite promising soft computing platform modelling the human brain, though currently only available as a software model. A second part of the paper therefore focuses on a possible VLSI architecture for hierarchical temporal memory. Since it models the human brain, communication as well as memory are of high importance for this VLSI architecture.

机译：与人脑相比，常规算法仍然无法轻松地执行许多现实世界中的应用程序，例如用户支持系统。近来，常常通过使用基于概率的系统来达到这种智能。本文介绍了在贝叶斯网络以及分层时间存储器上实现这样一个用户支持系统（即意向估计信息设备系统）的结果。后者是一个新的并且很有希望的软计算平台，它可以对人的大脑进行建模，尽管目前只能作为软件模型使用。因此，本文的第二部分重点介绍了用于分层时间存储器的可能的VLSI体系结构。由于它可以对人脑进行建模，因此通信和内存对于此VLSI架构都至关重要。

著录项

来源
《Multiple-Valued Logic, 2009. ISMVL '09》|2009年|233-238|共6页
会议地点 Naha(JP);Naha(JP)
作者
Melis W.J.C.; Chizuwa S.; Kameyama M.;
展开▼
作者单位

Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai;

展开▼
会议组织
原文格式 PDF
正文语种
中图分类
关键词
VLSI; belief networks; domestic appliances; home computing; knowledge based systems; Bayesian network; VLSI architecture; hierarchical temporal memory; intention estimation information appliance system; soft computing platform; user support system; probabilistic systems; soft computing; user support systems;

机译：VLSI;信念网络;家用设备;家庭计算;基于知识的系统;贝叶斯网络; VLSI体系结构;分层时间存储器;意图估计信息设备系统;软计算平台;用户支持系统;概率系统;软计算;用户支持系统;

相似文献

外文文献
中文文献
专利

1. Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access [J] . Masanori HARIYAMA, Member, Haruka SASAKI, IEICE Transactions on Information and Systems . 2005,第7期

机译：基于分层并行存储器访问的立体匹配VLSI处理器的体系结构
2. Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing [J] . Deliang Fan, Mrigank Sharad, Abhronil Sengupta, Neural Networks and Learning Systems, IEEE Transactions on . 2016,第9期

机译：基于自旋神经元和电阻记忆的分层时间记忆，用于高效节能的脑启发计算
3. A programmable VLSI architecture for computing multiplication and polynomial evaluation modulo a positive integer [J] . Lu E.-H., Harn L. IEEE Journal of Solid-State Circuits . 1988,第1期

机译：一种可编程的VLSI架构，用于计算乘积和多项式求模的正整数
4. Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and Its VLSI Architecture [C] . Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama IEEE International Symposium on Multiple-Valued Logic . 2009

机译：评估分层时间记忆作为软计算平台及其VLSI架构
5. Scalable Digital Architecture of Hierarchical Temporal Memory Spatial Pooler [D] . Praveen, Sadhvi. 2017

机译：分层时间记忆空间池的可扩展数字体系结构
6. On the Design of Efficient Hierarchic Architecture for Software Defined Vehicular Networks [O] . Muhammad Adnan, Jawaid Iqbal, Abdul Waheed, 2021

机译：关于软件定义车辆网络的高效分层体系结构设计
7. Evaluation of the hierarchical temporal memory soft computing platform and its VLSI architecture [O] . Melis W.J.C., Chizuwa S., Kameyama M. 2009

机译：分层时态存储器软计算平台及其VLSI架构的评估

Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

摘要

著录项

相似文献

相关主题

期刊订阅