• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文学位 >Scalable Digital Architecture of Hierarchical Temporal Memory Spatial Pooler
【24h】

Scalable Digital Architecture of Hierarchical Temporal Memory Spatial Pooler

机译：分层时间记忆空间池的可扩展数字体系结构

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Hierarchical Temporal memory is an unsupervised machine learning algorithm. Inspired by the structural and functional properties of the human brain, it is capable of processing spatio-temporal signals which are used for data storage and predictions. The algorithm is composed of two main components; the Spatial Pooler and the Temporal Memory. The spatial pooler produces a sparse distribution representation for the given pattern. These generalized representations are used by the temporal memory to make predictions. Therefore, it is important to ensure that more generalized sparse distribution representations are obtained for the spatio-temporal data patterns.;This work presents the digital design of spatial pooler implementation for an existing mathematical algorithm along with an analysis of its scalability for the target FPGA device. The digital design is implemented in two ways; Conventional and Parallel architectures. The architectures are compared in terms of speedup, area and power consumption. Based on the analysis of results, it is seen that the parallel approach is more efficient in terms of speed and power, with a negligible increase in device utilization. The spatial pooler design is evaluated against the standard MNIST dataset, obtaining up to 90% and 88% classication accuracy for the train and test data, respectively. Additionally, the designs are tested on the MNIST dataset, in the presence of noise, to determine its robustness. Fluctuations of up to 10% of the peak accuracy are observed during classication, and are noted in the classication accuracy plots for the dataset with noise. The design is synthesized for the Xilinx Virtex 7 family with a total power consumption of up to 260 mW.
机译：分层时间记忆是一种无监督的机器学习算法。受人脑的结构和功能特性启发，它能够处理时空信号，该信号用于数据存储和预测。该算法由两个主要部分组成：空间池和时间记忆。空间池生成器针对给定的模式生成稀疏分布表示。这些广义的表示由时间存储器用来进行预测。因此，重要的是要确保为时空数据模式获得更通用的稀疏分布表示形式。这项工作介绍了现有数学算法的空间池实现的数字设计，并分析了其在目标FPGA上的可扩展性设备。数字设计以两种方式实现：常规和并行体系结构。根据速度，面积和功耗比较了这些体系结构。根据结果​​分析，可以看出并行方法在速度和功率方面更为有效，而设备利用率的增加却可以忽略不计。针对标准MNIST数据集评估了空间池设计，分别为火车和测试数据获得了高达90％和88％的分类精度。另外，在存在噪声的情况下，对设计在MNIST数据集上进行测试以确定其鲁棒性。在分类期间观察到高达10％的峰准确度波动，并在带有噪声的数据集的分类准确度图中指出了这一点。该设计针对Xilinx Virtex 7系列进行了综合，其总功耗高达260 mW。

著录项

  • 作者

    Praveen, Sadhvi.;

  • 作者单位

    Rochester Institute of Technology.;

  • 授予单位 Rochester Institute of Technology.;
  • 学科 Computer engineering.
  • 学位 M.S.
  • 年度 2017
  • 页码 75 p.
  • 总页数 75
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 公共建筑;
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号