STRUCTURAL QUALITY AND ELECTRICAL BEHAVIOR OF EPITAXIAL HIGH-k Y_2O_3 / Si(001)

机译：表观高k Y_2O_3 / Si（001）的结构质量和电性能

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Y_2O_3 thin films were grown directly on Si (001) by MBE and annealed in-situ under UHV at various annealing temperatures. The samples were investigated in-situ by RHEED and ex-situ by HRTEM. A 7 to 15 A thick non-uniform interfacial amorphous layer is observed in the as-grown sample. After annealing at 490℃ under UHV for 30 minutes the amorphous layer is reduced and a sharp Y_2O_3/Si interface is obtained. At higher annealing temperatures, YSi_2 islands start to form at the Y_2O_3/Si interface. Ⅰ-Ⅴ measurements performed on generic MIS structures show that the annealed samples exhibit higher leakage current density than the as-grown sample, due to reduction of the wide band gap interfacial layer. Leakage current densities in annealed samples remain below 1A/cm~2, which is acceptable for future high-κ transistor fabrication.

机译：Y_2O_3薄膜通过MBE直接在Si（001）上生长，并在各种退火温度下的UHV下进行原位退火。样品通过RHEED进行了原位研究，并通过HRTEM进行了异位研究。在刚生长的样品中观察到7至15 A厚的不均匀界面非晶层。在490℃，超高压下退火30分钟后，非晶层被还原，并获得清晰的Y_2O_3 / Si界面。在较高的退火温度下，YSi_2岛开始在Y_2O_3 / Si界面处形成。对通用MIS结构进行的I-Ⅴ测量表明，由于宽带隙界面层的减少，退火样品的泄漏电流密度比生长的样品高。退火样品中的漏电流密度保持在1A / cm〜2以下，这对于将来的高k晶体管制造是可以接受的。

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来源
《Novel Materials and Processes for Advanced CMOS》|2002年|p.367-372|共6页
会议地点 Boston MA(US);Boston MA(US)
作者
G. Vellianitis; G. Apostolopoulos; A. Dimoulas; K. Argyropoulos; B. Mereu; R. Scholz; M. Alexe; J.C. Hooker;
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作者单位

MBE Laboratory, Institute of Materials Science, NCSR "Demokritos", Athens, GREECE;

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原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
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STRUCTURAL QUALITY AND ELECTRICAL BEHAVIOR OF EPITAXIAL HIGH-k Y_2O_3 / Si(001)

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