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Advanced 2D die placement inspection system for reliable flip chip interconnections based on 3D information of die and substrate by a phase measuring profilometry

机译:先进的2D芯片放置检查系统,用于通过相位测量轮廓仪,基于芯片和基板的3D信息,实现可靠的倒装芯片互连

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摘要

To use flip chip interconnection technology for semiconductor packages offers a number of possible advantages to the user: reduced signal inductance, reduced power/ground inductance, higher signal density, die shrink, and reduced package footprint. However, manufacturing processes for 'flip chip'-integrated packages need a high precision alignment between flip chip and matched substrate. Comparing with original visual alignment based on 2D image information, an advanced die placement inspection system for reliable flip chip interconnections has been firstly proposed by authors [2]. In this paper, the proposed system is reviewed briefly, and system calibration algorithms and information processing algorithms are described in detail. To verify the system performance, a series of real experiments is performed on flip chip packages for high performance
机译:将倒装芯片互连技术用于半导体封装为用户提供了许多可能的优势:降低了信号电感,降低了电源/接地电感,提高了信号密度,缩小了芯片尺寸并减少了封装面积。但是,集成“倒装芯片”封装的制造工艺需要在倒装芯片和匹配的基板之间进行高精度对准。与基于2D图像信息的原始视觉对齐方式相比,作者首先提出了一种用于可靠倒装芯片互连的先进芯片放置检查系统[2]。本文对提出的系统进行了简要回顾,并详细描述了系统校准算法和信息处理算法。为了验证系统性能,对倒装芯片封装进行了一系列实际实验以提高性能

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