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首页> 外文会议>Photomask and Next-Generation Lithography Mask Technology XIV pt.2; Proceedings of SPIE-The International Society for Optical Engineering; vol.6607 pt.2 >Implementation of Double Dipole Lithography for 45nm node poly and diffusion layer manufacturing with 0.93NA
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Implementation of Double Dipole Lithography for 45nm node poly and diffusion layer manufacturing with 0.93NA

机译：采用0.93NA的45nm节点多晶硅和扩散层制造双偶极光刻技术的实现

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The double dipole lithography (DDL) has been proven to be one of the resolution enhancement technologies for 45 nm node. In this paper, we have implemented a full-chip DDL process for 45nm node using ArF immersion lithography. Immersion exposure system can effectively enlarge the process DoF (depth of focus). Combining with dipole illumination can help us to reach smaller k1 value (～0.31) and meet the process requirements of poly and diffusion layers on 45nm node by using only 0.93 NA exposure tool. However, from a full-chip processing point of view, the more challenging question should be: how to calibrate a good model from two exposure and decompose original design to separate mask sets? Does the image performance achieve a production worthy standard? At 45nm node, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For DDL full-chip processing, we need a robust application strategy to ensure a very tight CD control. We implemented an integrated RET solution that combines DDL along with polarization, immersion system, and model based OPC to meet full-chip manufacturing requirement. This is to be a dual-exposure mask solution for 45nm node — X-dipole exposure for vertical mask and horizontal for Y-dipole. We show a rocess design flow starting from the design rule analysis, layout decomposition, model-based OPC, manufacturing reliability check, and then to the mask data preparation. All of the work has been implemented using MaskWeaver~TM geometry engine. Additionally, we investigated printability for through-pitch line features, ASIC logic, and SRAM cell design patterns. Different circuit layout needs dedicated special OPC treatment. To characterize the related process performance, we use mask enhancement error factor (MEEF), process window (PW), and critical dimension uniformity (CDU) to analyze the simulation data. Since we used the tri-tone Att-PSM, the mask making flow and spec was also taking into consideration. The device electrical performance was examined for production feasibility. We conclude that the DDL process is ready for 45nm node and is well within reach to be used on next generation production environment.
机译：双偶极光刻（DDL）已被证明是用于45 nm节点的分辨率增强技术之一。在本文中，我们使用ArF浸没光刻技术为45nm节点实现了全芯片DDL工艺。浸入式曝光系统可以有效地扩大制程的DoF（聚焦深度）。仅使用0.93 NA曝光工具，结合偶极照明可以帮助我们达到较小的k1值（〜0.31），并满足45nm节点上的多晶硅和扩散层的工艺要求。但是，从全芯片处理的角度来看，更具挑战性的问题应该是：如何从两次曝光中校准好模型，然后将原始设计分解为单独的掩模组？图像性能是否达到值得生产的标准？在45nm节点处，我们使用曝光波长的四分之一进行构图；错误的余地很小。对于DDL全芯片处理，我们需要一种可靠的应用策略来确保非常严格的CD控制。我们实现了集成的RET解决方案，该解决方案将DDL与极化，浸没系统和基于模型的OPC相结合，以满足全芯片制造要求。这将是针对45nm节点的双曝光掩模解决方案-X偶极曝光用于垂直掩模，水平X偶极用于Y偶极。我们展示了流程设计流程，该流程从设计规则分析，布局分解，基于模型的OPC，制造可靠性检查，再到掩模数据准备开始。所有工作已使用MaskWeaver〜TM几何引擎完成。此外，我们研究了节距线特性，ASIC逻辑和SRAM单元设计模式的可印刷性。不同的电路布局需要专用的特殊OPC处理。为了表征相关的工艺性能，我们使用掩模增强误差因子（MEEF），工艺窗口（PW）和临界尺寸均匀性（CDU）来分析仿真数据。由于我们使用了三色调Att-PSM，因此还考虑了掩模的制造流程和规格。检查设备的电气性能以生产可行性。我们得出结论，DDL工艺已经为45nm节点做好了准备，并且可以在下一代生产环境中使用。

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