Tunneling gate oxide MOSFET technology

机译：隧道栅氧化物MOSFET技术

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Characteristics of direct tunneling gate oxide MOSFETs are described. The effect of the gate leakage current on the MOSFET characteristics becomes small as gate length reduces. Extremely high DC and AC performances were realized using such an ultra-thin oxide down to 1.5nm. Higher reliability in hot-carier and TDDB has been also observed.

机译：描述了直接隧穿栅极氧化物MOSFET的特性。随着栅极长度的减小，栅极泄漏电流对MOSFET特性的影响变小。使用这种低至1.5nm的超薄氧化物，可实现极高的DC和AC性能。还观察到在热载运和TDDB中具有更高的可靠性。

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来源
《Proceedings of the 27th European solid-state device research conference》|1997年|p.133-142|共10页
会议地点 Stuttgart(DE);Stuttgart(DE)
作者
Hisayo Sasaki Momose; Shin-ichi Nakamura; Yasuhiro Katsumata; Hiroshi Iwai;
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原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
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专利

1. Calculation of direct tunneling gate current through ultra-thin oxide and oxide/nitride stacks in MOSFETs and H-MOSFETs [J] . E. Cassan, P. Dollfus, S. Galdin Microelectronics & Reliability . 2000,第4a5期

机译：通过MOSFET和H-MOSFET中的超薄氧化物和氧化物/氮化物叠层计算直接隧穿栅极电流
2. An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides [J] . Mondal I., Dutta A. K. IEEE Transactions on Electron Devices . 2008,第7期

机译：具有超薄栅极氧化物的MOSFET的分析栅极隧穿电流模型
3. Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide [J] . Momose H.S., Nakamura S.-I. IEEE Transactions on Electron Devices . 1998,第3期

机译：1.5纳米直接隧穿栅极氧化物MOSFET的制造可行性研究：栅极氧化物的均匀性，可靠性和掺杂剂渗透
4. Localization of NBTI-induced oxide damage in direct tunneling regime gate oxide pMOSFET using a novel low gate-leakage gated-diode (L/sup 2/-GD) method [C] . Chung, S.S., Lo, . 2002

机译：使用新型低栅漏栅二极管（L / sup 2 / -GD）的方法在直接隧穿区栅氧化物pMOSFET中NBTI引起的氧化物损伤的定位
5. Development of a process flow for self -aligned double -gate MOSFET by tunnel epitaxy using nitrided thermal oxide as gate insulators. [D] . Ahmed, Shibly Sadique. 2001

机译：通过隧道外延，使用氮化的热氧化物作为栅绝缘体，开发自对准双栅MOSFET的工艺流程。
6. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs [O] . H. Hussin, N. Soin, M. F. Bukhori, -1

机译：栅堆叠结构和工艺缺陷对32 nm工艺节点PMOSFET中NBTI可靠性的高k介电依赖性的影响
7. Back-Gated Buried Oxide MOSFET’s in a High-Voltage Bipolar Technology for Bonded Oxide/SOI Interface Characterization [O] . R. Bashir, F. Wang, W. Greig, 2015

机译：采用高压双极技术的背栅绝缘氧化物mOsFET，用于粘合氧化物/ sOI界面表征
8. Influence of the Polysilicon Gate on the Random Dopant Induced Threshold Voltage Fluctuations in Sub 100 nm MOSFETS with Thin Gate Oxides [R] . Asenov, Asen, Saini, S. 2000

机译：多晶硅栅极对具有薄栅氧化层的亚100nm mOsFET中随机掺杂诱导阈值电压波动的影响

Tunneling gate oxide MOSFET technology

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