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首页> 外文会议>Proceedings of the 46th Annual Design Automation Conference >A trace-capable instruction cache for cost efficient real-time program trace compression in SoC
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A trace-capable instruction cache for cost efficient real-time program trace compression in SoC

机译：具有跟踪功能的指令高速缓存，可在SoC中实现经济高效的实时程序跟踪压缩

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This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time program trace compressor. This goal is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. The trace compression works in both the bypass mode and the online mode. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource. The RTL implementation of a 4KB trace-capable instruction cache, a 4KB data cache and an academic ARM7 processor core has been accomplished. The experiments show that the cache achieves average compression ratio of 90% with a very small hardware overhead of 3652 gates. In addition, the trace support circuit does not impact the global critical path. Therefore, the proposed approach is highly feasible on-chip debugging/monitoring solution for SoCs, even for cost sensitive ones such as consumer electronics.
机译：本文提出了一种新颖的方法，可以使SoC的片上指令高速缓存同时充当常规指令高速缓存和实时程序跟踪压缩器。该目标是通过利用指令高速缓存的字典功能以及附加在高速缓存侧面的小型支持电路来实现的。跟踪压缩在旁路模式和在线模式下均有效。与相关工作相比，这项工作具有利用现有指令高速缓存的优势，这在现代SoC中是必不可少的，因此可以节省大量的硬件资源。 RTL实现了4KB具有跟踪功能的指令高速缓存，4KB数据高速缓存和学术性的ARM7处理器内核。实验表明，高速缓存以3652门的极小的硬件开销实现了90％的平均压缩率。此外，跟踪支持电路不会影响全局关键路径。因此，所提出的方法对于SoC来说是高度可行的片上调试/监视解决方案，甚至对于成本敏感的消费电子产品也是如此。

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