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首页> 外文会议>Proceedings of the 46th Annual Design Automation Conference >Double patterning lithography friendly detailed routing with redundant via consideration
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Double patterning lithography friendly detailed routing with redundant via consideration

机译：双图案光刻友好的详细布线，并考虑了冗余

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摘要

In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achieve high quality solution for DPL-unfriendly designs, due to complex 2D patterns in lower metal layers. Therefore, DPL-friendliness is needed at routing stage [3]. Another key yield improvement technique is redundant via insertion [4] [5]. However, this would increase the complexity in DPL-compliance. To make designs manufacturable in DPL, we should not insert a redundant via if it results in coloring conflict. This paper is the first work to consider DPL and redundant via together. We have developed two algorithms, post-routing DPL-aware insertion and DPL-friendly routing with redundant via consideration to take into account redundant via DPL-compliance. Experimental results show that, compared to a DPL-aware optimization flow without redundant via consideration, we can improve insertion rate by 43% while still achieving zero coloring conflicts. Moreover, we can reduce the number of vias and stitches by 9% and 17% respectively.
机译：在双图案光刻（DPL）中，着色冲突和针迹最小化是两个主要挑战。布局后分解算法[1] [2]可能不足以实现DPL不友好设计的高质量解决方案，这是由于较低金属层中的复杂2D图案。因此，在路由阶段[3]需要DPL友好性。另一种提高产量的关键技术是通过插入[4] [5]实现冗余。但是，这会增加DPL遵从性的复杂性。为了使设计可在DPL中制造，如果导致颜色冲突，则不应插入多余的过孔。本文是同时考虑DPL和冗余的第一篇论文。我们已经开发了两种算法，即路由后的DPL感知插入和DPL友好路由，并考虑了通过DPL遵从性带来的冗余性，从而实现了冗余。实验结果表明，与无需考虑冗余的DPL感知优化流程相比，我们可以将插入率提高43％，同时实现零着色冲突。此外，我们可以将通孔和针脚数量分别减少9％和17％。

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