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首页> 外文会议>Proceedings of the 46th Annual Design Automation Conference >Analysis and mitigation of process variation impacts on Power-Attack Tolerance
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Analysis and mitigation of process variation impacts on Power-Attack Tolerance

机译：分析和缓解工艺变化对功率攻击容限的影响

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Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impact the data-dependent power of deep submicron cryptosystem designs. In this paper, we use Monte Carlo methods in SPICE circuit simulations to analyze the statistical properties of the data-dependent power with predictive 45nm CMOS device and ITRS process variation models. In addition to the "measurement to disclosure" (MTD) used in [3], we define a lower level metric, Power-Attack Tolerance (PAT), to model both dynamic power and leakage power data-dependence. We show that the PAT of a typical cryptographic component implementation using CMOS standard-cells can significantly deteriorate due to process variations, thus increasing the component's vulnerability to power attacks. Power-attack-resistant logic styles (e.g. SABL [9]) have been developed which increase PAT by an order of magnitude by balancing power consumptionat the gate level with considerable overhead. However in the presence of process variations, the degradation probability of MTD is 57%. To mitigate this problem, we demonstrate a transistor sizing optimization method that can reduce such negative impacts to only 18% with minimal power and area overhead.
机译：嵌入式密码系统显示出对实施攻击（例如功率分析）的漏洞增加。 CMOS技术趋势正在导致工艺变化的增加，从而影响深亚微米密码系统设计的数据相关能力。在本文中，我们在SPICE电路仿真中使用了Monte Carlo方法，以预测性的45nm CMOS器件和ITRS工艺变化模型来分析数据相关功率的统计特性。除了在[3]中使用的“公开度量”（MTD）之外，我们还定义了一个较低级别的度量，即Power-Attack Tolerance（PAT），以对动态功率和泄漏功率数据相关性进行建模。我们显示，由于工艺变化，使用CMOS标准单元的典型加密组件实现的PAT可能会严重恶化，从而增加了组件遭受电源攻击的脆弱性。已经开发了抗电源攻击的逻辑样式（例如SABL [9]），该逻辑样式通过平衡门级的功耗和相当大的开销将PAT提高了一个数量级。但是，在存在工艺变化的情况下，MTD的降级概率为57％。为了缓解这个问题，我们展示了一种晶体管尺寸优化方法，该方法可以将这种负面影响降低到18％，同时功耗和面积开销最小。

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