DEVICE AND SUBSTRATE DESIGN FOR SUB-10 NM MOSFETS

机译：低于10 NM MOSFET的器件和衬底设计

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CMOS devices will be scaled to sub-10 nm gate lengths in the next decade. Functional transistor with 6 nm gate length has been demonstrated using ultrathin channel structure. However, to continue the device performance trend, carrier mobility must be increased with the technology. We discuss various mobility enhancement techniques through device and substrate design.

机译：未来十年，CMOS器件的栅极长度将缩小至10 nm以下。使用超薄沟道结构已证明了栅极长度为6 nm的功能晶体管。但是，要继续保持设备性能趋势，必须通过该技术提高运营商的移动性。我们讨论通过设备和基板设计的各种迁移率增强技术。

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《Proceedings vol.2004-01; International Symposium on Advanced Short-Time Thermal Processing for Si-Based CMOS Devices II; 20040510-12; San Antonio,TX(US)》|2004年|P.371-382|共12页
会议地点 San AntonioTX(US)
作者
Meikei Ieong; Bruce Doris; Jakub Kedzierski; Zhibin Ren; Ken Rim; Min Yang; Huiling Shang; Leland Chang;
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IBM Semiconductor Research and Development Center (SRDC), Microelectronic Division, Hopewell Junction, NY, USA;

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正文语种 eng
中图分类半导体技术;
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DEVICE AND SUBSTRATE DESIGN FOR SUB-10 NM MOSFETS

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