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Novel backside sample preparation processes for advanced CMOSintegrated circuits failure analysis

机译:用于高级CMOS 集成电路故障分析的新型背面样品制备过程

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Backside sample preparation techniques are reported for advancednintegrated circuits (ICs) packaged in conventional wire-bond ceramic andnplastic packages as well as in flip-chip packages. Backside samplenpreparation is an enabling step to other backside FA techniques such asninfrared (IR) emission microscopy and IR-based internal signal voltagenprobing. The sample preparation steps involve heat sink/package milling,nand silicon substrate thinning and polishing. In addition, the use of annantireflection coating (ARC) layer to improve the success rate andnsensitivity of backside photo-emission microscopy is presented
机译:已报道了用于以常规引线键合陶瓷和塑料封装以及倒装芯片封装的先进集成电路(IC)的背面样品制备技术。背面样品制备是其他背面FA技术(例如红外(IR)发射显微镜和基于IR的内部信号电压探测)的一个使能步骤。样品制备步骤包括散热器/封装铣削,硅基板减薄和抛光。此外,还介绍了使用反反射涂层(ARC)来提高背面光发射显微镜的成功率和灵敏度的问题。

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