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首页> 外文会议>SEMICON China 2004 Technical Programs >Testing Challenges of Device Synchronous Buses
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Testing Challenges of Device Synchronous Buses

机译：测试设备同步总线的挑战

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Serial buses operating in the Gbps range are becoming common on today’s integrated circuits (ICs) and are expected to become even more prevalent in the near future. These device-synchronous buses present unique problems for production testing due to the high speed of data, necessity for clock recovery, and the non-deterministic nature of the communication protocols. The traditional tester-synchronous method of digital testing is no longer effective, forcing automatic test equipment (ATE) suppliers to provide a new generation of digital pin cards to address these types of buses. This paper discusses the unique challenges posed by device synchronous buses as well as the resulting requirements of production test equipment. The PCI Express [1] standard is used to illustrate specific examples of testing a high-speed serial bus. The paper also presents new solutions for testing devices containing high-speed serial buses. Functionally testing the protocol state machine and multi-time domain functional testing for complex devices with asynchronous buses is discussed. This paper also addresses lowering the cost-of-test with a single instrument that supports multiple protocols and multiple clocking schemes.
机译：在Gbps范围内运行的串行总线在当今的集成电路（IC）中变得越来越普遍，并且有望在不久的将来变得更加流行。由于数据的高速，时钟恢复的必要性以及通信协议的不确定性，这些设备同步总线为生产测试提出了独特的问题。传统的测试仪同步数字测试方法不再有效，迫使自动测试设备（ATE）供应商提供新一代的数字针卡来解决这些类型的总线。本文讨论了设备同步总线带来的独特挑战以及对生产测试设备的最终要求。 PCI Express [1]标准用于说明测试高速串行总线的特定示例。本文还提出了用于测试包含高速串行总线的设备的新解决方案。讨论了功能测试协议状态机和具有异步总线的复杂设备的多时域功能测试。本文还致力于通过支持多种协议和多种时钟方案的单一仪器来降低测试成本。

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