Low area FSM-based memory BIST for synchronous SRAM

机译：基于FSM的低面积存储器BIST，用于同步SRAM

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As the memory enters submicron technology, new test algorithm that will be able to give a better fault coverage such as to detect all intra-word coupling fault (CF) has been widely developed. In order to implement this algorithm to the memory, test technique such as BIST is utilized. Common types of memory built-in-self test (MBIST); microcode-based MBIST and FSM-based MBIST. The popular approach of designing various kind of MBIST architectures are either by targeting to reach specific testing requirement such as on full speed and at speed or by considering the cost-constraint and area overhead such low-cost or low-area design. In this paper, FSM-based BIST is designed to be able detecting all intra-word coupling fault (CF) in a synchronous SRAM under low-area constraint of test requirement.

机译：随着存储器进入亚微米技术，新的测试算法将能够提供更好的故障覆盖率，例如检测所有字内耦合故障（CF）。为了将该算法实现到存储器，利用了诸如BIST的测试技术。常见的内存内置自我测试类型（MBIST）；基于微码的MBIST和基于FSM的MBIST。设计各种MBIST架构的流行方法是针对特定的测试要求（例如全速和全速），或者考虑成本约束和面积开销（例如低成本或小面积设计）。在本文中，基于FSM的BIST被设计为能够在测试需求的小范围约束下检测同步SRAM中的所有字内耦合故障（CF）。

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来源
《Signal Processing amp; Its Applications, 2009. CSPA 2009》|2009年|409-412|共4页
会议地点 Kuala Lumpur(MY);Kuala Lumpur(MY)
作者
Noor N.Q.M.; Yusof Y.; Saparon A.;
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Dept. of Electron., Univ. Teknol. MARA, Shah Alam;

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SRAM chips; built-in self test; fault diagnosis; finite state machines; logic testing; finite state machine; intra-word coupling fault; low area FSM-based memory BIST; memory built-in-self test; microcode-based MBIST; synchronous SRAM;

机译：SRAM芯片;内置自检;故障诊断;有限状态机;逻辑测试;有限状态机;字内耦合故障;基于FSM的低面积内存BIST;内存内置自检;基于微码的MBIST;同步SRAM;

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1. CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks [J] . Biswas Avishek, Chandrakasan Anantha P. IEEE Journal of Solid-State Circuits . 2019,第1期

机译：CONV-SRAM：具有低功耗卷积神经网络内存中点积计算功能的节能SRAM
2. Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems [J] . JOYDEEP RAKSHIT, KARTIK MOHANRAM, RUNLAI WAN, ACM Journal on Emerging Technologies in Computing Systems . 2017,第2期

机译：单层晶体管SRAM：朝向低功耗，更密集的内存系统
3. cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System [J] . J. Wang, L. Wang, H. Yin, IEEE Transactions on Computers . 2016,第4期

机译：cNV SRAM：基于CMOS技术的基于非易失性SRAM的超低泄漏能量混合存储系统
4. Low Area FSM-Based Memory BIST for Synchronous SRAM [C] . Nur Qamarina Mohd Noor, Yusrina Yusof, Azilah Saparon International Colloquium on Signal Processing Its Applications . 2009

机译：基于低区域FSM的内存BIST用于同步SRAM
5. Low power and process variation aware SRAM and Cache design fault tolerance in SRAM circuit, architecture and organization. [D] . Sasan, Avesta. 2010

机译：低功耗和工艺变化感知型SRAM和Cache在SRAM电路，架构和组织中的设计容错能力。
6. Synchronous and opposite roles of the parietal and prefrontal cortices in bistable perception: a double-coil TMS-EEG study [O] . Marine VERNET, Anna-Katharine BREM, Faranak FARZAN, -1

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7. CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks [O] . Avishek Biswas, Anantha P. Chandrakasan 2019

机译：CONV-SRAM：具有用于低功耗卷积神经网络的内存点的节能SRAM
8. SEU (Single Event Upset) Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM (Static Random Access Memories) [R] . Weaver, H. T. , Axness, C. L. , McBrayer, J. D. , 1987

机译：sEU（单事件翻转）容忍存储器单元源自sRam中的sEU机制的基础研究（静态随机存取存储器）

Low area FSM-based memory BIST for synchronous SRAM

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